Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-29
2004-11-23
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180
Reexamination Certificate
active
06822910
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a structure of a non-volatile memory and an operating method thereof. More particularly, the present invention relates to a structure of a non-volatile memory that stores one bit per cell (1 bit/cell) and an operating method thereof.
2. Description of Related Art
In the family of non-volatile memory devices, various electrically erasable programmable read-only memory (E
2
PROM) devices have been widely used in personal computers and electronic apparatuses since they can be programmed, erased and read repeatedly, and can retain data even if disconnected from electrical power. A conventional E
2
PROM adopts a floating gate and a control gate both made from doped polysilicon. After the E
2
PROM is programmed by charge injection, the charges distribute evenly in the floating gate. Therefore, a leakage easily occurs in a memory cell if there are defects in its tunnel oxide layer under the floating gate, and the reliability of the device is lowered.
To solve the leakage problem of the conventional E
2
PROM, a charge-trapping layer is recently developed to replace the polysilicon floating gate used in the conventional flash memory. The charge-trapping layer usually comprises a silicon nitride layer that is disposed between two silicon oxide layers to form an oxide
itride/oxide (ONO) composite structure, while the memory with such a charge-trapping layer is known as a “nitride read-only memory (NROM)”.
An NROM can be programmed with channel hot electron injection (CHEI) mechanism, wherein appropriate biases are applied to the gate and the source/drain of the NROM cell. If the bias on the drain is higher than that on the source, hot electrons are generated in the channel near the drain and injected into the nitride charge-trapping layer. Since the nitride charge-trapping layer is able to trap electrons, the injected electrons will not distribute evenly in the charge-trapping layer, but will be localized in a region of the charge-trapping layer near the drain. Because the injected electrons are localized, the charge-trapping region is small and is less likely to locate on the defects of the tunnel oxide layer. A leakage therefore does not easily occur in the device.
FIG. 1
illustrates a local circuit diagram of a conventional NROM array, which is also disclosed in U.S. Pat. No. 5,966,603. The memory array illustrated in
FIG. 1
is a 3×3 array that includes memory cells Qn
1
~Qn
9
coupled to word lines WL
01
~WL
03
, bit lines BL
1
and BL
2
, and source lines SL
1
and SL
2
. The drains of Qn
1
, Qn
4
and Qn
7
are coupled to BL
1
, and the drains of Qn
2
, Qn
3
, Qn
5
, Qn
6
, Qn
8
and Qn
9
are coupled to BL
2
. The sources of Qn
1
, Qn
2
, Qn
4
, Qn
5
, Qn
7
and Qn
8
are coupled to SL
1
, and the sources of Qn
3
, Qn
6
and Qn
9
are coupled to SL
2
. The gates of the memory cells in the same row are connected to a word line, i.e., the gates of Qn
1
~Qn
3
are coupled to WL
01
, the gates of Qn
4
~Qn
6
to WL
02
, and the gates of Qn
7
~Qn
9
to WL
03
.
Referring to
FIG. 1
, in each row of memory cells, the gates of the cells are coupled to the same word line, each cell shares its source and drain with two adjacent cells, and the sources or drains of the cells are coupled to different source lines or bit lines. Since a memory cell shares a word line and its source/drain with other cells, it is necessary to apply different biases to different source lines or bit lines as a specific memory cell is to be programmed, and the programming process therefore is quite complicated.
For example, when the source side of Qn
5
is being programmed, WL
02
, SL
1
and BL
2
are applied with 5V, 5V and 0V, respectively, to induce band-to-band hot hole phenomenon and thereby inject hot holes into the charge trapping layer on the source side. However, at the same time, the bit line BL
1
coupled to Qn
4
must be applied with 3V to prevent programming of Qn
4
since Qn
4
and Qn
5
both are coupled to the same word line WL
02
and the same source line SL
1
. Similarly, when the drain side of Qn
5
is being programmed, WL
02
, BL
2
and SL
1
are applied with 5V, 5V and 0V, respectively, to induce band-to-band hot hole phenomenon and thereby inject hot holes into the charge trapping layer on the drain side. However, at the same time, the source line SL
2
coupled to Qn
6
must be applied with 3V to prevent programming of Qn
6
since Qn
6
and Qn
5
both are coupled to the same word line WL
02
and the same bit line BL
2
. Accordingly, the programming process is quite complicated.
On the other hand, since the conventional NROM array uses buried source lines and buried bit lines that have high resistance, the operating speed of the memory device is not easy to raise.
SUMMARY OF INVENTION
Accordingly, this invention provides a non-volatile memory and the operating method thereof, wherein the programming operation of a single memory cell does not interfere with other memory cells.
This invention also aims to provide a non-volatile memory and the operating method thereof that allow a programming operation with one bit, one byte or one sector as a unit.
This invention further provides a non-volatile memory and the operating method thereof to increase the operation speed of the memory device.
The non-volatile memory device of this invention comprises a plurality of memory cells, a plurality of word lines, a plurality of drain lines and a plurality of source lines, wherein two adjacent memory cells in a column constitute a cell pair, and all cell pairs are arranged in rows and columns. The two memory cells in each cell pair share a source region, and two adjacent cell pairs in a column share a drain region. The source regions and the gates of the memory cells in the same row are coupled to a source line and a word line, respectively, and the drain regions of the memory cells in the same column are coupled to a drain line.
Accordingly, the source lines are parallel to the word lines and perpendicular to the drain lines in the non-volatile memory of this invention. Therefore, a low power operation frequently used in localized charge storage memory devices is particularly suitable for the non-volatile memory. That is, the non-volatile memory device can be erased with Fowler-Nordheim (FN) tunneling mechanism, programmed with band-to-band hot hole injection mechanism on the source side, and read from the opposite drain side.
Moreover, the sources of the memory cells in the same column are coupled to different source lines, so the programming operation of a single memory cell does not interfere with other memory cells.
In the non-volatile memory of this invention, the source line and the drain line can comprise a low-resistance material such as metal. Since the sources/drains of the memory cells in the same rows/columns are electrically connected to a source/drain line, the resistance of the memory array is lower and the operating speed is higher as compared with a conventional memory array using buried bit lines and buried source lines.
Moreover, since the non-volatile memory of this memory does not use buried bit lines, the sources/drains can be formed after the word lines are formed and the manufacturing process thus is more compatible with conventional CMOS process.
Furthermore, in this invention, an isolation can be formed between columns of memory cells, and spacers can be formed on the sidewalls of the gates of the memory cells. With the isolation and the spacers, the contacts between the sources/drains and source/drain lines can be formed as borderless contacts.
This invention also provides an operating method of the aforementioned non-volatile memory of this invention. In an erasing operation, the selected word line is applied with a first positive voltage, and the p-well of the selected cells (sector), the selected drain lines and the selected source lines are applied with 0V to erase the selected memory cells with channel FN tunneling mechanism. In a programming operation, the selected word line is applied with a
Lu Tao-Cheng
Tsai Wen-Jer
Yeh Chih-Chieh
Hoang Huan
Jianq Chyun IP Office
Macronix International Co. Ltd.
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