Semiconductor device having damascene interconnects

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

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Details

257751, 257760, 257763, 257764, 257768, 257774, H01L 2348, H01L 2352, H01L 2940

Patent

active

057083037

ABSTRACT:
This is a device and method of optimizing capacitance and performance for multilevel interconnects. The device comprising: a semiconductor layer 70; a first high-k layer 68 above the semiconductor layer; a first insulating layer 66 above the first high-k layer 68; an interconnect layer 58 above the first insulating layer 66; a second insulating layer 64 around the interconnect layer 58; and a second high-k layer 52 above the second insulating layer 64 and the interconnect layer 58. The device may have a low-k material inserted between closely spaced metal interconnects. Alternatively, the device may have air gaps between closely spaced metal interconnects. In addition, the first high-k layer may be used as an oxide etch stop.

REFERENCES:
patent: 4613888 (1986-09-01), Mase et al.
patent: 4618878 (1986-10-01), Aoyama et al.
patent: 5216281 (1993-06-01), Butler
patent: 5319246 (1994-06-01), Nagamine et al.
patent: 5345108 (1994-09-01), Kikkawa

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