Start-up circuit

Details Start-up circuit Start-up circuit

2002-09-24

2004-02-17

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S198000

Reexamination Certificate

active

06693471

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
The present application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2001-293892, filed Sep. 26, 2001, which is herein incorporated by reference in its entirely for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a start-up circuit, and more particularly to a start-up circuit generating and outputting an initialization signal which initializes an internal circuit of a semiconductor integrated circuit when a power supply voltage is supplied to the internal circuit.
2. Description of the Related Art
FIG. 5
is a circuit diagram showing a conventional start-up circuit
500
. The conventional start-up circuit
500
includes a power supply node T
1
to which is a power supply voltage VCC, a ground node T
2
to which a ground voltage GND, a node n
1
, a PMOS transistor
501
located between the power supply node T
1
and the node n
1
, a condenser C
51
located between the node n
1
and the ground node T
2
, an inverter INV
1
having PMOS and NMOS transistors
503
and
505
, an inverter INV
2
having PMOS and NMOS transistors
507
and
509
, and an output node ST. The inverter INV
1
is located between the power supply and ground nodes T
1
and T
2
, and receives a signal from the node n
1
. The inverter INV
2
is located between the power supply and ground nodes T
1
and T
2
, and receives an output signal of the inverter INV
1
.
Charging of the condenser C
51
starts when the power supply voltage VCC is supplied to the power supply node T
1
. Then, a voltage level of the node n
1
rises in response to a time constant on the basis of an ON state resistance of the PMOS transistor
501
and a capacity of the condenser C
51
. Since a charged voltage level of the condenser C
51
is low right after the power supply voltage VCC is supplied to the power supply node T
1
, the voltage level of the node n
1
is initially a low (“L”) level. As a result, since the PMOS transistor
503
assumes an ON state and the NMOS
505
assumes an OFF state, an output signal of the inverter INV
1
is a high (“H”) level. Therefore, the PMOS transistor
507
of the inverter INV
2
assumes an OFF state and the NMOS transistor
509
assumes an ON state, and then an “L” level signal is outputted from the output node ST. Then, the condenser C
51
is further charged. A “H” level signal is eventually outputted from the output node ST after the voltage level of the node n
1
becomes higher than a threshold voltage level of the inverter INV
1
.
Accordingly, after the power supply voltage VCC is supplied to the power supply node T
1
, the voltage level of the output node ST is maintained at an “L” level for a certain period in response to the time constant, and is then switched to an “H” level after the certain period. An initialization of an internal circuit which is connected to the output node ST is performed during the certain period that the voltage level of the output node ST is at the “L” level.
An electrical charge stored in the condenser C
51
discharges to the power supply node T
1
through the PMOS transistor
501
, when a supply of the power supply voltage VCC to the power supply node T
1
is (interrupted) stopped.
However, during a discharge of the condenser C
51
of the conventional start-up circuit, since the PMOS transistor
501
switches to an off state when a voltage level of the node n
1
falls to a threshold voltage level of the PMOS transistor
501
, an electrical charge having the threshold voltage level of the PMOS transistor
501
is still held in the condenser C
51
. Such an electrical charge discharges during a state in which the power supply voltage VCC is disrupted. However, a discharging time of the electrical charge becomes to longer. Also, since the electrical charge stored in the condenser C
51
does not discharge quickly when the power supply voltage VCC is disrupted, an electrical potential is held at the node n
1
. Then, if a supply of the power supply voltage VCC is resumed, the voltage level of the node n
1
exceeds the threshold voltage level of the inverter INV
1
before initialization of the internal circuit. As a result, an “H” level signal is outputted from the output node ST before the internal circuit can be initialized properly.
SUMMARY OF THE INVENTION
The present invention is therefore directed to providing a start-up circuit which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
It is an objective of the invention to provide a start-up circuit, in which a power supply node which receives a power supply voltage, a ground node which receives a ground voltage, a first node, a first capacitor which is located between the first node and the ground node, a supply circuit which is located between the power supply node and the first node, and which supplies an electrical charge from the power supply node to the first capacitor, a discharge circuit which is located between the first node and the ground node, and which discharges an electrical charge stored in the first capacitor to the ground node, and an output circuit which is connected to the first node, and which outputs a start-up signal when a voltage level of the first node becomes higher than a set voltage level.
According to the present invention, even though the supply of the power supply voltage to the power supply node is disrupted, a period of charging the electrical charge into the condenser can be sufficiently secured. Therefore, a period of initializing the internal circuit electrically connected to the output node ST can be sufficiently secured.
The present invention can shorten the recovery period from the release of the disruption of the supply of the power supply voltage, until the termination of the reset signal. Therefore, the present invention can achieve a reduction in power consumption of the integrated circuit.
The above and further objects and novel features of the invention will become more fully apparent from the following detailed description, appended claims and accompanying drawings herein.


REFERENCES:
patent: 5892381 (1999-04-01), Koifman et al.
patent: 6285223 (2001-09-01), Smith
patent: 6597215 (2003-07-01), Wang

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