Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-07-31
2004-11-02
Awad, Amr (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S212000, C345S213000
Reexamination Certificate
active
06812915
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device, and more particularly to an active matrix liquid crystal display including a pluraliyt of pixels having a switching element each.
FIG. 1
shows the configuration of a conventional active matrix liquid crystal display device (AM-LCD). This AM-LCD displays images by receiving the signals: a vertical synchronizing signal V
sync
, a horizontal synchronizing signal H
sync
, a dot clock, and picture signals. These signals come from a personal computer or the like.
A liquid crystal display panel
1
includes thin film transistors (TFTs)
12
liquid crystal capacitors
13
, storage capacitors
14
for improving the quality of displayed images, and gate lines
15
, and source lines
16
. A gate line
15
is connected to the gate electrodes of the TFTs for supplying a scanning signal to the transistors. A source line
16
is connected to the source electrodes of the TFTs for supplying a signal voltage to the TFTs. The gate lines
15
are connected to a gate driver
2
, and the source lines
16
to a source driver
3
.
The AM-LCD receives the vertical synchronizing signal V
sync
, the horizontal synchronizing signal H
sync
, the dot clock and the picture signals (display data) synchronized with the dot clock, thereby displaying images on the display panel
1
. Specifically, display data corresponding to one horizontal line are stored in the source driver
3
during one horizontal synchronizing period. The stored display data corresponding to one horizontal line are outputted all at once to the source lines of the liquid crystal display panel
1
during the next horizontal synchronizing period. As a scanning signal is inputted to a gate line at the same time, the TFTs on the gate line are turned on and supply electric charges corresponding to the display data to the liquid crystal capacitors. This operation is carryed out for each gate line, and a whole image can be displayed on the display panel.
The functions of the control sections for signals given to the gate driver
2
and the source driver
3
will be described next.
A register
4
holds in advance a value as the counted number of horizontal synchronizing signal pulses corresponding to the period from the switching timing of the vertical synchronizing signal to the starting timing of an effective display data period. A register
5
holds in advance a value as the counted number of dot clock pulses corresponding to the period from the switching timing of the horizontal synchronizing signal to the starting timing of an effective display data period.
A start pulse generation circuit
6
generates a gate start pulse signal and a source start pulse signal for giving start timings to the gate driver
2
and the source driver
3
respectively, on the basis of the signal V
sync
, the signal H
sync
, the dot clock and the values held in the respective registers
4
and
5
. The gate start pulse signal and the source start pulse signal from the start pulse generating circuit
6
determine a display area on the liquid crystal display panel
1
.
On the other hand, a start pulse generation circuit
7
generates a gate start pulse signal and a source start pulse signal for giving start timings for the gate driver
2
and the source driver
3
respectively, on the basis of a data enable signal indicating effective display data periods comming from an computer and the signal V
sync
. The gate start pulse signal and the source start pulse signal from the start pulse generating circuit
7
determine a display area on the liquid crystal display panel
1
. Thus the start pulse generating circuit
7
enables the AM-LCD to control the display area from the outside as far as the horizontal direction is concerned.
The gate start pulse signal generated by the start pulse generation circuits
6
or
7
is inputted to the gate driver
2
through a selector
9
, and the source start pulse signal generated by the circuits
6
or
7
is inputted to the source driver
3
through a selector
8
. Each of the selectors
8
and
9
selects these start pulse signals in response to a select signal from a computer.
A circuit
10
converts picture signals (display data) into A.C. signals in a specified a frequency (for example, 50 or 60 Hz) and sends them to the source driver
3
.
There are two modes for displaying images; one is the display fixing mode, in which the display area is fixed on a specified position, and the other is the display control mode, in which the display area can be controlled signals from the outside. The operations according to these display modes will now be described as follows.
(1) Display Fixing Mode
FIG. 2A
shows a timing chart for describing the operation of this mode. Referring to the register
4
holding the value, the start pulse generation circuit
6
counts the pulses of the signal H
sync
, with the switching timing of the signal V
sync
as a starting point, and generates a gate start pulse signal V
sp1
on the completion of counting up to the value. In other words, the gate start pulse signal V
sp1
is generated after a lapse of a specified length of time V
bp
(shown in
FIG. 2A
) from the switching timing of the signal V
sync
.
Besides, referring to the register
5
holding the value, the start pulse generation circuit
6
counts the pulses of the dot clock pulses (not shown) with the switching timing of the signal H
sync
as a starting point and generates the source start pulse signal H
sp1
on the completion of counting up to the value. In other words, the source start pulse signal H
sp1
is generated after a lapse of a specified length H
bp
(shown in
FIG. 2A
) from the switching timing of the signal H
sync
.
While a select signal that indicates the display fixing mode is being inputted to the selectors from a computer, the signal V
sp1
and the signal H
sp1
that are generated by the start pulse generating circuit
6
are selected by the selectors
8
and
9
, and being inputted to the gate driver
2
and the source driver
3
.
The source driver
3
starts to output the stored display data A, B, C, D, E, . . . to the source lines in synchronism with the H
sp1
on receiving the signal V
sp1
. At the same time, the gate driver
2
starts to output scanning signals G
1
, G
2
, G
3
, G
4
, . . . sequentially to the gate lines in synchronism with the H
sp1
. As a result, a whole image including the display data A, B, C, D, E, . . . can be displayed in a specified position on the liquid crystal display panel
1
.
(2) Display Control Mode
A data enable signal indicating effective display data periods keeps an enable level during an effective display data period, and keeps a disable level during an invalid display data period. As shown in
FIG. 2B
, a source start pulse signal H
sp2
is generated at the timing when the data enable signal goes to the enable level. Besides, a gate start pulse signal V
sp2
is generated at the timing when the data enable signal goes to the enable level after the first pulse of the signal H
sp2
.
While the select signal indicating the display control mode is being inputted to the selectors from a computer, the signal V
sp2
and the signal H
sp2
that are generated by the start pulse generating circuit
7
are selected by the selectors
8
and
9
and being inputted to the gate driver
2
and the source driver
3
, respectively.
The source driver
3
starts to output the stored display data A, B, C, D, E, . . . to the source lines in synchronism with the signal H
sp2
on receiving the signal V
sp2
. At the same time, the gate drives
2
starts to output the scanning signals G
1
, G
2
, G
3
, G
4
, . . . , sequentially to the gate lines in synchronism with the signal H
sp2
. As a result, a whole image including the display data A, B, C, D, E, . . . , can be displayed in a desired position on the liquid crystal display panel
1
.
Thus, two interface signals, namely, the data enable signal and the select signal are necessary for the display control mode in addition to the five signals: the signal V
sync
, the signal
Awad Amr
NEC LCD Technologies Ltd.
Whitham Curtis & Christofferson, PC
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