Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-12-11
2004-11-16
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S109000, C257S689000, C257S777000, C257S786000
Reexamination Certificate
active
06818474
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor package, and more particularly, to a method for manufacturing a stacked chip package having a stacked structure comprising a plurality of semiconductor chips.
2. Description of the Related Art
Recently, electronic apparatuses have a small size and a simple structure and therefore, it is required to develop a package having high density and high mount rate. And, according to increased memory capacity, a chip size is increased such as Random Access Memory (RAM) and Flash Memory, however, a package size becomes small.
There are several methods proposed to reduce a package size, including a Multi Chip Package (MCP) and Multi Chip Module (MCM) comprising a plurality of chips and packages. However, the above methods have limitations in production since semiconductor chips and packages are arranged on a substrate in a plane mode.
In order to overcome the limitations, a staked chip package has been proposed, which is formed by stacking a plurality of chips having the same memory capacity.
The stacked chip package has several advantages including low manufacturing cost due to simplified process and mass production, and at the same time disadvantages of small area for inner lead due to increased chip size.
FIG. 1
is a cross sectional view showing a conventional method for manufacturing a stacked chip package.
As shown in
FIG. 1
, the conventional stacked chip package
100
has a structure that a plurality of semiconductor chips
120
,
130
and
140
are mounted on a substrate
110
in a plane mode.
The semiconductor chips
120
,
130
and
140
are attached on the mounting region of the substrate
110
by an adhesive
114
and a plurality of bonding pads
122
,
132
and
142
are formed on a backside to the side attached to the substrate
110
. The semiconductor chips
120
,
130
and
140
are arranged in a step shape and the bonding pads
122
,
132
and
142
are formed on the edge of the semiconductor chips
120
,
130
and
140
.
And, bonding wires
124
,
134
and
144
are formed to electrically connect the bonding pads
122
,
132
and
142
and a conductive pattern
112
.
In order to protect connecting parts on the semiconductor chips
120
,
130
and
140
and the substrate
110
, epoxy resin is sealed, thereby completing a package body
150
.
The conductive pattern
112
of substrate
110
is an interconnection layer for the electrical connection of the semiconductor chips
120
,
130
and
140
and a solder ball
160
.
The semiconductor chips
120
,
130
and
140
are electrically connected with each other by a circuit pattern formed on the substrate
110
or bonding pads
122
,
132
and
142
are bonded to boding wires
124
,
134
and
144
by the conductive pattern
112
to accomplish electrical connection.
However, the stacked chips have different size and they are stacked only in a face-up direction on the edge by bonding pads, thereby it is difficult to be applied to chips having the same size and bonding pads arranged on the center of semiconductor chip.
And, it is impossible to increase the number of stacked chip leads in the conventional method. As a result, there is a problem that a NC pin is additionally required since Chip Select Pins (CS pin) of top chips and bottom chips are slit, one of which is connected to CS pin and the other to NC pin.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made in an effort to solve the problems occurring in the related art, and an object of the present invention is to provide a method for manufacturing a stacked chip package having a bonding pad on the center part and stacking the same size semiconductor chips in both a face up and a face down modes.
In order to achieve the second object, the present invention comprises the steps of: attaching a first substrate including a first center window on a first semiconductor chip having a plurality of bonding pads arranged on the center part; forming a first bonding wire connecting the first semiconductor chip and the first substrate; attaching a second substrate including a second center window on a second semiconductor chip having a plurality of second bonding pads on the center part; forming a second bonding wires connecting the second semiconductor chip and the second substrate; attaching the backsides of the resulting first and the second semiconductor chips; forming a third bonding wire connecting the first and the second substrates; forming a molding body overlaying the first, the second and the third bonding wires; and adhering a conductive ball to the first substrate.
The present method further comprises the steps of forming a first and a second bars for fixing the position on the backsides of the, first and the second substrates to the side where the first and the second center windows are formed.
The first and the second bars for fixing the position are formed of solder resist.
The first and the second bars for fixing the position have a thickness of 20 &mgr;m to 1 mm.
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Kim Ji Yon
Moon Ki Ill
Hynix / Semiconductor Inc.
Ladas & Parry LLP
Thomas Toniae M.
Wilczewski Mary
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