Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Quality evaluation
Reexamination Certificate
2002-02-22
2004-02-03
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Quality evaluation
C716S030000
Reexamination Certificate
active
06687633
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an inspection system that manages a particle or a pattern defect generated in a production process of an electronic device, such as a semiconductor integrated circuit, a thin film magnetic head, and an optical device, or an inspection apparatus that detects the particle or the pattern defect, and a production method that uses it.
BACKGROUND OF THE INVENTION
A prior art is described below taking the production of a semiconductor integrated circuit as an example. The semiconductor integrated circuit (hereinafter referred to as LSI) is generally divided into the front-end process in which a layer, such as a circuit pattern, is multiply layered on a silicon wafer and multiple chips (elements) are manufactured and the succeeding process in which the layer is isolated for each chip and products are completed. The greater part of faults that will be generated during production is generated in the huge front-end process accompanied by microfabrication. Accordingly, the improvement of yield in the front-end process is a very important issue for low cost production. Here, the yield in the front-end process is good product ratio determined based on the result of a probing test that is the final test of the front-end process, that is, a ratio of good chips to the total number of chips on the wafer.
The faults of the front-end process can roughly be divided into a functional fault and a parametric fault. The functional fault indicates a fault in which a particle or a pattern defect (hereinafter generically referred to as a defect) generated in the course of production becomes the main cause, which will cause the disconnection and short circuit of a circuit pattern and will not operate a circuit normally. On the other hand, the parametric fault is a fault in which the operation speed of a transistor will not satisfy a design specification due to fine process dispersion, such as fabrication dimensions or oxide film thickness.
In order to detect the particles or the pattern defects that cause the functional fault, a defect inspection tool, such as a dark-field inspection tool or a bright-field inspection tool is used in the front-end process production line. The dark-field inspection tool, as described in Japanese Patent No.2533610, generally, irradiates a wafer with laser beam and detects the scattered light. The bright-field inspection tool, as described in Japanese Patent No.2981434, photographs an image of a circuit pattern and detects abnormal spots by image processing.
In order to detect the particles or the pattern defects that cause the functional fault, a defect inspection tool, such as a dark-field inspection tool or a bright-field inspection tool is used in the preprocess production line. The dark-field inspection tool, as described in Japanese Patent No.2533610, generally, irradiates a wafer with laser beam and detects the scattered light. The bright-field inspection tool, as described in Japanese Patent No.2981434, photographs an image of a circuit pattern and detects abnormal spots by image processing.
The production line manages the number of defects detected usually by the defect inspection tool to maintain yield. This is based on a concept that the yield can be maintained highly by stably holding the number of defects. However, because an interrelationship is not necessarily established between the number of defects and the yield, it is not said the best policy to manage the number of defects. This is because a degree (yield loss) in which the yield deteriorates differs according to the size and type of the generated defect and the process or position in which the defect was generated.
One method by which the result of a defect inspection is converted to a yield loss and managed is disclosed in Japanese Patent Laid-open No. 2000-223385. This method associates the result of a probing test and the result of a defect inspection every LSI chip and computes the yield loss limited by defects. However, this method requires the result of a probing test that is the final test of the front-end process every wafer and the yield loss will not output immediately after a defect inspection. Accordingly, the problem was that time is required until the yield loss is computed.
Another method by which the result of a defect inspection is converted to a yield loss and managed observes individual defects through an electron microscope after defect inspection and classifies the defects into a fatal defect and a non-fatal defect, then manages the number of fatal defects. This method does not require the result of the probing test if the accuracy of classification is high and can obtain the yield loss after the defects are observed. However, because an LSI circuit pattern is scaled down and a defect inspection tool is made high accurate, the number of defects detected by the defect inspection tool is continuing a great increase. Accordingly, it is difficult due to the time limit to observe and classify all defects through the electron microscope.
As an attempt that solves these problems, a method by which the yield loss is predicted from the result of a defect inspection is proposed. The typical method is called a critical area analysis. The critical area analysis is described in Japanese Patent Laid-open No.Sho48-40376, Japanese Patent Laid-open No.Hei08-162510, U.S. Pat. No. 5,598,341, and the paper “Modeling of Defects in Integrated Circuit Photolithographic Patterns” run in the monographs “IBM Journal of Research and Development” (Volume 28, No.4, 1984). This method has a supposition that defects are generated in random points and the distribution of defect size is fixed. That the distribution of defect size is fixed is premised on an assumption that if there are a small number of large defects and a great number of small defects, the relationship is always invariable. However, defects that will be generated on an actual wafer will not always be generated in random points. Further, the size distribution is not fixed, and only the small defects may also be generated frequently. Accordingly, the critical area analysis had the problem of prediction accuracy.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above circumstances and provides an inspection system, an inspection apparatus, an inspection program, and a production method of semiconductor devices.
The present invention converts a yield loss at high accuracy from the result of a defect inspection without waiting for the result of a probing test. Further, even if defects are not observed through an electron microscope, the yield loss can be converted. In a production line, such a strategy that chiefly analyses and manages an apparatus of the production process for which a measure must be taken can be worked out.
Further, a critical area analysis that is a conventional yield loss prediction art had a precondition that defects are generated in random points or the distribution of defect size is fixed. However, the present invention does not have such precondition, and is effective even if the defects are not generated in the random points. Further, even if the distribution of defect size differs every wafer, prediction accuracy will not be decreased.
As a means for solving the above issue, first, one example is an inspection system provided with an analyzing unit that has an inspection apparatus that detects the position and size of particles or pattern defects that an inspected object has, a storage means that is connected to the inspection apparatus via a network and stores inspection data that the inspection apparatus detected and obtained and kill ratio computation data for the position and size of the particles or pattern defects set in a device formed in the inspected object, and a computation means that computes kill ratios of individual particles or pattern defects from the inspection data that the inspection apparatus detected and obtained and the kill ratio computation data and kill ratios of individual chips of the inspected object from the kill rati
Iwata Hisafumi
Ono Makoto
Barlow John
Hitachi , Ltd.
McDermott & Will & Emery
Sun Xiuqin
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