Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2003-08-04
2004-08-24
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C438S015000
Reexamination Certificate
active
06781232
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed to an apparatus and method for preparing semiconductor devices for analysis and more specifically pertains to the creation of transparent inspection windows in chips to permit examination of their circuitry while fully functional.
Semiconductor devices are typically encapsulated in resin or ceramic which serves to protect the device and to positively fix in position the conductor leads that extend therefrom. The resin or ceramic capsule serves as a hermetically sealed barrier that has high mechanical strength and is substantially impervious to most chemicals. In order to conduct construction analysis and failure analysis it is absolutely essential for such encapsulation, or at least a portion of such encapsulation, to be removed. Moreover, it is necessary for the integrity and full functionality of the chip to be maintained despite such decapsulation.
Various techniques have been developed for use in evaluating the structure and functions of a semiconductor chip. For example, an image emission microscope may be employed to localize defects in integrated circuits. The utility of the emission microscope is based on the principle of recombinant radiation. In excess current drawing conditions such as occur during semiconductor failure modes, electrons and holes in silicon, recombine and relax, giving off a photon of light which is readily detectable by specialized intensified CCD sensors. Such emissions are non-isotropic and therefore radiate toward the front as well as the back of the die. The predominant value of the technique is rapid detection and failure localization to the junction level of a single transistor in integrated circuits which may include up to 4,000,000 or more transistors. Infrared and thermal techniques have also been developed for the purpose of inspecting chips and identifying failures. Common to all such visualization techniques is the fact that the silicon in the chip acts as a filter for such radiation, and must therefore be thinned in order for a sufficient degree of transparency to be achieved. Gaining access to the silicon die for the purpose of thinning further requires that the plastic encapsulation be removed.
Various decapsulation (or depacking) techniques have been developed in order to gain access to the underlying chip along with techniques with which the thickness of the silicon die can then be reduced. Heretofore used approaches are however all subject to various shortcomings. Planar lapping with diamond slurries allows the requisite thinning to be achieved but because the entire device is lapped, the leads must be bent out of the way and once the lead frame becomes thinned, the leads cannot be bent back to their original configuration without breakage. This in turn precludes socket testing which poses a considerable hardship especially when high lead count devices are involved. Additionally, because the entire wafer must be thinned to the desired depth, the structural integrity of the device becomes severely compromised which renders the subsequent handling and testing of the device difficult. Reagent thinning is possible, but only hydrofluoric acid is capable of effectively dissolving the silicon and hydrofluoric acid is extremely hazardous. Dimpling techniques have also been employed wherein a slow speed grinding wheel extending from a weighted head is spun against the workpiece which is also being slowly spun. This results in a bowl shaped cut known as a dimple having a flat area surrounded by a radiused edge. The inspection area is therefore limited as the regions outside the flatspot abruptly lose contrast due to increasing silicon thickness. Radiused edges cannot be avoided using this technique and larger flat spots can only be achieved by boring successively larger “test holes.” The technique is extremely time consuming and can take hours to cut through the packaging material and silicon. Ion milling techniques employing a focused ion beam have also been used with some success but are very slow and only capable of milling out a very tightly defined small area which requires detailed knowledge of the failure site. Such equipment is extremely expensive and requires the work to be performed under a high vacuum. Conventional milling techniques are effective for removing the packaging material but attempts to thin the die typically leads to chipping, gouging and cracking. Even at lower speeds, with the die supported by molding compound, the die tends to shatter. Modification of conventional milling techniques to substantially increase torque and rotational speeds (40,000 to 60,000 rpm) has been found effective to address the problem of breakage but the heat generated by such approach is substantial and requires the use of complex and bulky cooling equipment to prevent damage. Additionally, the extremely high precision with which the position of the cutting tool must be controlled requires the reliance on expensive CNC capability.
An improved approach is therefore needed with which access to the circuitry in packaged microchips can be gained relatively quickly and easily using relatively simple and inexpensive machinery.
SUMMARY OF THE INVENTION
The apparatus and method of the present invention provides an improved approach for thinning selected portions of semiconductor devices so as to render them transparent to infra-red light and thereby enable failure analysis to be carried out using emission microscopy (photon and thermal) as well as infra-red microscopy. The present invention provides for the thinning of an isolated portion or of portions of the backside of packaged devices so as to preserve wiring external to the die intact. The apparatus and method can also effectively be used to gain access to the front side of certain devices including circuit delayering. The thinning may be accomplished in packaged semiconductor devices as well as of single dies (or small groups of dies) and of specific areas on multi-chip modules.
The present invention provides for the controlled grinding and polishing of the targeted areas so as to remove a very precise amount of material in a minimal amount of time while at the same time minimizing the generation of heat. Elements of polishing and milling techniques are combined to prevent the semiconductor device from being heat damaged without the need for complex cooling equipment to thereby greatly reduce cost and complexity. Moreover, the invention provides a degree of precision and reproducibility in the formation of an access window in a semiconductor device that had not previously been available.
The invention provides for the oscillation of the semiconductor device in the X-Y plane while a sequence of rotating tools are applied against the device along. The tools are rotated about the Z axis and float along such axis to engage the workpiece under a selectable constant force. The configurations of the tools are selected as a function of the composition of the particular material of the semiconductor device that is to be removed. The force with which a selected tool is brought to bear against the surface of the material device remains constant and a broad range of forces is available for selection. Those tools that are applied under a relatively light constant force have a radial surface with which material is removed while the tools that are rotated at relatively high constant force have a circumferential surface with which material is removed. The apparatus of the present invention allows the force that is applied to be quickly and easily adjusted and allows the speed of rotation to be adjusted. Additionally, the apparatus includes an oscillating table component to which the semiconductor device is positively affixed. The amplitude of the oscillations is adjustable. The tilt of the table is also adjustable about both the X direction and Y direction, to compensate for common angular error in the assembly operation so as to maintain the planar relationship between the working surface of the tool and the workpiece.
Prior to the actual removal
Fulwider Patton Lee & Utecht LLP
Hoang Quoc
Nelms David
Ultra Tec Manufacturing, Inc.
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