Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-03-28
2004-10-12
Nguyen, Jimmy H. (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S067000, C345S068000
Reexamination Certificate
active
06803888
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of driving a plasma display panel, and particularly to a method of driving an AC plasma display panel.
2. Description of the Related Art
Plasma display panels (hereinbelow abbreviated “PDP”) typically offer many features including thin construction, lack of flicker, and a high display contrast ratio, and in addition are relatively amenable to large screen applications. They have a high response speed, and in emissive types can emit color visible lights using phosphors. As a result, plasma display panels increasingly are becoming widely used in recent years in the fields of computer-related display devices and color image display devices.
Depending on the mode of operation, PDP can be divided between an AC type, in which AC discharge occurs indirectly between electrodes that are covered by a dielectric material, and a DC type, in which discharge occurs by exposing electrodes in a discharge space.
The AC type can be further divided between the memory type that takes advantage of the memory effect of the display cells, and the refresh type that does not use the memory effect.
The luminance of the PDP is proportional to the number of discharges, i.e., the number of repeated pulses applied within a prescribed time interval (for example, one frame). Luminance drops as the capacitance of the display increases in the above-described refresh type, and this type is therefore chiefly used for a PDP having a low display capacitance.
The structure of a display cell of the above-described AC memory-type PDP is first described using FIG.
1
.
As shown in
FIG. 1
, a display cell of an AC memory-type PDP is made up of: first insulating substrate
1
and second insulating substrate
2
that are composed of glass and provided on the rear and front surfaces of the panel; transparent scan electrodes
3
and sustain electrodes
4
that are formed on second insulating substrate
2
at a prescribed spacing; first trace electrodes
5
and second trace electrodes
6
that are each laminated so as to overlap over scan electrodes
3
and sustain electrodes
4
, respectively, so as to decrease the electrode resistance of scan electrodes
3
and sustain electrodes
4
; first dielectric layer
12
that is formed to cover each of scan electrodes
3
, sustain electrodes
4
, first trace electrodes
5
, and second trace electrodes
6
; protective layer
13
laminated on first dielectric layer
12
composed of, for example, magnesium oxide, for protecting first dielectric layer
12
from discharges; data electrodes
7
arranged on first insulating substrate
1
and formed in a direction that is orthogonal to scan electrodes
3
and sustain electrodes
4
; second dielectric layer
14
formed to cover data electrodes
7
; discharge gas space
8
that is formed between first insulating substrate
1
and second insulating substrate
2
and that is filled with a discharge gas composed of an inert gas such as helium, neon, or xenon, or a gas mixture of these gases; barrier ribs
9
provided on second dielectric layer
14
for both forming discharge gas spaces
8
and demarcating discharge cells; and phosphor
11
applied onto second dielectric layer
14
and to the sides of barrier ribs
9
for converting ultra-violet rays generated by discharge in discharge gas space
8
into visible light
10
.
In an actual PDP such as a color display panel for VGA, the above-described display cells are arranged in a lattice pattern with 480 display cells in the vertical direction and 1920 display cells in the horizontal direction, 480 scan electrodes
3
and 1920 sustain electrodes
4
being arranged corresponding to these cells.
The discharge in a PDP constructed as shown in FIG.
1
is next explained.
Discharge begins inside the display cell shown in
FIG. 1
when a pulse voltage that exceeds the discharge threshold value is applied between scan electrode
3
and data electrode
7
, whereupon a positive or negative charge (wall charge) according to the polarity of this pulse voltage is attracted to and accumulated on the surface of first dielectric material
12
and second dielectric material
14
.
Since the equivalent internal voltage that is generated as a result of the accumulation of this charge, i.e., the wall voltage, is of the opposite polarity of the applied pulse voltage, the effective voltage inside the cell drops with the growth of discharge. Discharge therefore cannot be sustained and eventually stops even if the above-described pulse voltage is maintained at a fixed value.
Subsequent application of a sustain pulse, which is a pulse voltage of the same polarity as the wall voltage, between scan electrode
3
and sustain electrode
4
causes a build-up in the wall voltage as the effective voltage, which thereby exceeds the discharge threshold value to bring about discharge even if the voltage amplitude of the sustain pulse applied from the outside is small. In other words, discharge is sustained by continuing to apply sustain pulses between scan electrode
3
and sustain electrode
4
.
The above-described sustain discharge can be stopped by applying to scan electrode
3
or to sustain electrode
4
a sustain erase pulse, which is a either a wide low-voltage pulse or a narrow pulse of approximately the same voltage as the sustain pulse that serves to neutralize the wall voltage.
As shown in
FIG. 2
, a PDP is a display panel capable of dot matrix display in which display cells
20
are arranged in a lattice of m rows and n columns. The PDP is provided with scan electrodes Sc
1
, Sc
2
, . . . Scm, and sustain electrodes Su
1
, Su
2
, . . . , Sum, that are arranged parallel to each other as row electrodes, and data electrodes D
1
, D
2
, . . . Dn that are arranged as column electrodes orthogonal to the scan electrodes and sustain electrodes.
When causing any display cell
20
to emit light, scan pulses are sequentially applied to scan electrodes Sc
1
, Sc
2
, . . . , Scm, and a data pulse that is in synchronism with the scan pulses is selectively applied to data electrode Di (1≦i≦n) that is to emit light, thereby applying a voltage that exceeds the discharge threshold value (hereinbelow, referred to as “writing display data”). Emission of light is then sustained by subsequently applying sustain pulses to sustain discharge between scan electrodes Sc
1
, Sc
2
, . . . Scm and sustain electrodes Su
1
, Su
2
, . . . , Sum.
As shown in
FIG. 3
, the PDP drive circuit is made up of: scan electrode drive circuit
21
for applying pulse voltages to each of scan electrodes Sc
1
, Sc
2
, . . . , Scm; sustain electrode drive circuit
22
for applying pulse voltages to each of sustain electrodes Su
1
, Su
2
, . . . , Sum; data electrode drive circuit
23
for applying a voltage in accordance with image signals to each of data electrodes D
1
, D
2
, . . . , Dn; and control circuit
24
for outputting control signals to the drive circuit of each electrode based on basic signals (vertical synchronizing signals Vsync, horizontal synchronizing signals Hsync, display data signals DATA, and Clocks).
The vertical synchronizing signals Vsync prescribe the period of one frame; and the horizontal synchronizing signals Hsync are for establishing synchronization in the horizontal direction, similar to the horizontal synchronizing signals that are the control signal of a CRT (Cathode-Ray Tube). The display data signals DATA are signals for prescribing whether each display cell
20
is to emit light or not emit light in accordance with image signals, and the Clocks are signals synchronized with display data signals DATA for causing display data signals DATA to be taken into control circuit
24
.
Control circuit
24
is made up of: frame memory
25
for temporarily storing display data signals DATA; memory control unit
26
for reading display data signals DATA from frame memory
25
and transferring display data signals DATA to data electrode drive circuit
23
in accordance with the timing of writing to the PDP; driver control unit
28
for gene
Nakamura Tadashi
Shimizu Masahiro
NEC Corporation
Nguyen Jimmy H.
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