Method of forming a shallow trench isolation

Details Method of forming a shallow trench isolation Method of forming a shallow trench isolation

2002-01-07

2004-10-26

Goudreau, George A. (Department: 1763)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S692000, C438S704000, C438S749000, C438S734000, C438S714000, C438S696000

Reexamination Certificate

active

06809004

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a trench isolation, and more particularly to a method for forming a shallow trench isolation capable of reducing a liner dent.
2. Description of the Related Art
Generally, an isolation structure in semiconductor processing is achieved by performing a thermal field oxidation process, such as a local oxidation of silicon (LOCOS) process. According to the LOCOS process, a pad oxide layer and a nitride layer are sequentially formed on a silicon substrate, and then, the nitride layer is patterned. A field oxide layer is formed by selectively oxidizing the silicon substrate using the patterned nitride layer as an anti-oxidation mask. When the silicon substrate is selectively oxidized, oxygen penetrates into a lateral side of the oxide layer from a lower portion of the nitride layer, which is used as the mask, so a “bird's beak” is created at an end portion of the field oxide layer. Accordingly, the field oxide layer expands towards an active area by a length of the bird's beak, so a width of the active area is reduced, such that the electrical characteristics of the semiconductor device are degraded.
For this reason, a shallow trench isolation (STI) structure was suggested in an ultra large-scale integrated semiconductor device. According to the STI process, a trench is formed by etching a silicon substrate. Then, an oxide layer is deposited to fill the trench. Thereafter, the oxide layer except in the trench is etched away by performing an etch back process or a chemical mechanical polishing (CMP) process, thereby forming a field oxide layer in the trench.
FIGS. 1A
to
1
D are sectional views showing a method for forming a conventional shallow trench isolation. Referring to
FIG. 1A
, a pad oxide layer is formed on a silicon substrates
10
. Then, a nitride layer and a high temperature oxide layer are sequentially deposited on the pad oxide layer. The nitride layer acts as a stopping layer when a chemical mechanical polishing process is carried out and the high temperature oxide layer acts as a hard mask layer.
Then, silicon oxynitride (SiON) is deposited on the high temperature oxide layer to form an anti-reflective layer (not shown). Then, a photolithography process for defining an active pattern is carried out to form a high temperature layer pattern
16
.
A nitride layer pattern
14
and a pad oxide layer pattern
12
are formed by etching the nitride layer and the pad oxide layer using the high temperature oxide layer pattern
16
as an etching mask. Then, an upper portion of the silicon substrate
10
adjacent to the nitride layer pattern
14
is etched to form a trench
18
.
In order to cure the damage of silicon caused by an impact of ions having high energy during the trench etching process, an exposed portion of the trench
18
is heat-treated in an oxidation atmosphere. Then, a trench inner wall oxide layer
20
is formed at an inside surface of the trench
18
including a bottom surface and a sidewall of the trench
18
caused by the oxidation reaction between exposed silicon and an oxidant in the oxidation atmosphere. Thereafter, a nitride layer liner
22
is deposited on the resulting structure in order to prevent current from leaking and to improve the characteristic of the gate oxide layer. If necessary, an oxide layer
23
is deposited on the nitride layer liner
22
to prevent the nitride layer liner
22
from being damaged when a gap filling oxide layer is deposited.
Referring to
FIG. 1B
, after forming the oxide layer
23
through the CVD process so as to fill the trench
18
, the CVD-oxide layer
23
is removed by the CMP process until the upper surface of the nitride layer pattern is exposed. As a result, a field oxide layer
24
is formed in the trench
18
.
Referring to
FIG. 1C
, the nitride layer pattern
14
is removed by performing a phosphoric acid stripping process. Generally, the polishing features of the CMP process vary on the basis of size, density and stepped portions of a pattern consisting an under-layer. Accordingly, the amount of polishing of the CVD-oxide layer
23
is varied at each region of the wafer when the CMP process is carried out due to the variation of the density of the active pattern, that is the nitride layer pattern
14
, formed under the CVD-oxide layer
23
. As a result, not only is the thickness of the nitride layer pattern
14
differently formed, but also the thickness of the field oxide layer
24
is different.
The nitride layer pattern
14
is removed by considering the maximum thickness of the nitride layer pattern
14
when the phosphoric acid stripping process is carried out. At this time, an over etch process is performed to completely remove the nitride layer pattern
14
. When the over etch process is carried out, the nitride layer liner
22
formed at the sidewall of the trench
18
is etched by the phosphoric acid so a liner dent (indicated by the symbol “A” in
FIG. 1C
) is created at a surface boundary between the active area and the field area after the phosphoric acid stripping process has been finished.
FIG. 1D
is an enlarged sectional view showing the surface boundary portion A formed between the active area and the field area.
FIG. 1D
shows a step of forming a gate oxide layer
26
on a surface of the active area after performing a wet cleaning process. The field oxide layer
24
is removed by a thickness of 200 to 500 Å when the stripping process and the cleaning process with respect to the nitride layer pattern
14
are performed. In addition, the liner dent created during the phosphoric acid stripping process grows when the cleaning process is carried out, so a groove G is formed in the field oxide layer
24
. The groove G causes leakage current.
In order to solve the above problems, a pull back process for the nitride layer liner has been suggested. Hereinafter, the pull back process will be described with reference to
FIGS. 2A
to
2
F.
Referring to
FIG. 2A
, a pad oxide layer is formed on a silicon substrate
50
. Then, a nitride layer and a high temperature oxide layer are sequentially deposited on the pad oxide layer. The nitride layer acts as a stopping layer when the CMP process is carried out and the high temperature oxide layer acts as a hard mask layer.
Then, silicon oxynitride (SiON) is deposited on the high temperature oxide layer to form an anti-reflective layer (not shown). Thereafter, a photolithography process for defining an active pattern is carried out to form a high temperature layer pattern
56
. A nitride layer pattern
54
and a pad oxide layer pattern
52
are formed by etching the nitride layer and the pad oxide layer using the high temperature oxide layer pattern
56
as an etching mask. Then, an upper portion of the silicon substrate
50
adjacent to the nitride layer pattern
54
is etched to form a trench
58
. At this time, the critical dimension of a bar of the nitride layer pattern
54
is identical to the critical dimension of an active bar.
Referring to
FIG. 2B
, the wafer is dipped in phosphoric acid for 6 seconds. Then, the nitride layer pattern
54
is etched in vertical and horizontal directions, so the critical dimension (a) of the bar of the nitride layer pattern
54
becomes smaller than the critical dimension (b) of the active bar.
Referring to
FIG. 2C
, in order to cure the damage of silicon caused by an impact of ions having high energy during the trench etching process, an exposed portion of the trench
58
is heat-treated in an oxidation atmosphere. Then, a trench inner wall oxide layer
60
is formed at an inside surface of the trench
58
including a bottom surface and a sidewall of the trench
58
caused by the oxidation reaction between exposed silicon and an oxidant in the oxidation atmosphere. Then, a nitride layer liner
62
is deposited on the resulting structure in order to prevent leakage current and to improve the characteristic of the gate oxide layer.
Referring to
FIG. 2D
, after forming the oxide layer
63
throu

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