Layout of a decoder and the method thereof

Details Layout of a decoder and the method thereof Layout of a decoder and the method thereof

2002-01-15

2004-10-19

Nguyen, Cuong (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257S208000

Reexamination Certificate

active

06806515

ABSTRACT:

This application incorporates by reference Taiwanese application Serial No. 90101196, filed on Jan. 18, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a layout of a decoder and the method thereof, particularly to the layout of a decoder and the method with fewer masks and smaller circuit width.
2. Description of the Related Art
A LCD (Liquid Crystal Display) has a data driver and a scan driver. Colors or images on the display are transformed by the following mechanism. First, one of the scan lines, which are needed to be scanned, is determined by the scan driver. Then, all the pixels in one of the scan lines are updated by inputting data signals from the data driver. Take the color TFT LCD (thin film transistor LCD) for example, each pixel includes three sub-pixels wherein the gray scale of each sub-pixel is controlled by a TFT (Thin Film Transistor). The three sub-pixels represent three colors of red, green and blue, respectively. Therefore, color of each pixel is controlled by three TFTs.
FIG. 1
shows the structure of driving circuit for a color TFT LCD
100
. When the resolution of the color LCD is achieved by 1280 pixels×1024 lines, 3840 (1280×3) sub-pixels as well as TFTs for each scan line are required. Firstly, the data driver
106
receives digital image data D and transfers digital image data D to analog image data by DAC
108
(Digital to Analog Converter, D/A). Then, the scan driver
104
selects scan line
114
(m) and the data of the sub-pixel on scan line(m) is updated through the data line
112
from the data driver
106
.
In the LCD, each sub-pixel contains liquid crystal to decide transmittance thereof and the transmittance is controlled by the voltage applied to the liquid crystal. If the voltage with the same polarity is constantly applied to the sub-pixel, liquid crystal will be easily damaged. The transmittance of each sub-pixel is related to the value of the applied voltage, not the polarity of the applied voltage. Therefore, the damage problem can be solved by polarity inversions.
FIG. 2
shows the circuit block diagram according to the DAC
108
in FIG.
1
. DAC
108
comprises a plurality of P-type DAC unit
202
, a plurality of N-type DAC unit
204
, a plurality of buffer unit
206
, switch units
210
and
212
. The P-type DAC unit
202
includes a plurality of PMOS (P-type Metal-Oxide-Semiconductor), and the N-type DAC unit
204
includes a plurality of NMOS (N-type Metal-Oxide-Semiconductor). These P-type and N-type DAC units are arranged alternately, and they are used for outputting different voltage levels. As the digital image data D of a scan line is inputted to the DAC unit
108
, the digital data D(n) for each sub-pixel is selected by the switch unit
210
, according to the dot inversion method or column inversion method, to input to the P-type DAC unit
202
or N-type DAC unit
204
. If the digital data D(n) is inputted to the P-type DAC unit
202
, the digital data D(n) will be transferred to an analog signal Vp. If the digital data D(n) is inputted to the N-type DAC unit
202
, the digital data D(n) will be transferred to an analog signal Vn. Thereafter, the analog signal Vp and Vn are inputted to the buffer unit
206
and the output signal Vp′ and Vn′ are produced, respectively. Next, the switch unit
212
outputs these output signal Vp′ and Vn′ to one of the data lines according to the method used by switch unit
210
. For the skilled in the art, it is well known that the analog signal Vp′ and Vn′ are the voltage with different polarity.
FIG. 3
shows the circuit diagram of N-type DAC unit
204
in FIG.
2
. Herein, the input of 3-bit is illustrated, and the digital data D(n) of 3-bit is provided. N-type DAC unit
204
comprises a resistor string Rs, an output line OUT and a decoder
302
. The two ends of the resistor string Rs are respectively connected to the voltage Vc and Vd. The resistor string Rs is composed of R
0
to R
6
which are connected in series. Therefore, 8 kinds of different voltage level from V(
0
) to V(
7
) are provided.
Decoder
302
is composed of a plurality of transistor node
310
and a plurality of channel node
320
in the array arrangement. The gate of transistor in each column of the transistor node
310
are connected with each other, and thereby the decoder inputs of B(
0
) to B(
5
) are produced. The source/drain of transistor Q in each row of the transistor node
310
and the channel node
320
are connected in series, and thereby the signal lines L(
0
) to L(
7
) are formed.
Please refer to FIG.
4
A and
FIG. 4B
at the same time. They show the circuit diagram of the transistor node
310
which contains a transistor Q and the circuit diagram of the channel node
320
which contains a connection line K, respectively. The decoder inputs B(
0
) to B(
5
) are used to receive the digital data D(n). The digital data D(n) b
0
′, b
0
, b
1
′, b
1
, b
2
′, b
2
are inputted to the decoder input B(
5
) to B(
0
), respectively, wherein b
0
, b
1
, b
2
are inverse of b
0
′, b
1
′, b
2
′. The input ends of the signal lines L(
0
) to L(
7
) are coupled with the output ends of the resistor string Rs. All of the output ends of the signal lines L(
0
) to L(
7
) are commonly connected to the output line OUT. Output line OUT is used to output the analog signal while the digital data are processed by the digital-to-analog conversion. The voltages V(
0
) to V(
7
) outputted from the resistor string Rs are inputted to the signal lines L(
0
) to L(
7
). The gates of the transistors on the signal lines L(i) are controlled by the decoder input B. When the transistors on the signal line L(i) are conducted, the output line OUT outputs voltage V(i). Meanwhile, only the transistors on the output line OUT are conducted, and only the input ends and the output ends on the signal line L(i) are conducted, wherein the
0
←i←
7
. For example, as the digital data D(n) is 000,—all of b
0
′, b
1
′ and b
2
′ are 1, only the transistors on the signal line L(
0
) are conducted. Therefore, the output line OUT outputs the analog signal Vn of voltage V(
0
).
FIG. 5
shows the layout of the decoder
302
in
FIG. 3
according to the conventional method. The layout of each transistor node
310
for the decoder
302
comprises a gate
530
, a source region
532
and a drain region
534
, which correspond to a transistor area. Other than the gate
530
, the source region
532
and the drain region
534
, the layout of the channel node
320
further comprises a doped layer
526
, which forms a short circuit between the source region
532
and the drain region
534
of the channel node
320
, and make the transistor always conduct. The channel node
320
corresponds to a channel area.
FIG. 6A
to
FIG. 6E
show manufacturing method for the signal line L(
0
) in FIG.
5
. The manufacturing process for the decoder
302
is as following. As show in
FIG. 6A
, a substrate
624
is provided. Then, a doped layer
526
is formed in the channel area as shown in FIG.
6
B. Next, the transistors are formed in whole transistor nodes
310
and whole channel nodes
320
of the decoder
302
, which corresponds to
FIG. 6C
to FIG.
6
E. In
FIG. 6C
, an oxide layer
628
is formed on the substrate
624
. As shown in
FIG. 6D
, a plurality of gates
530
are formed on the oxide layer
628
, and the source region
532
and drain region
534
are formed in the substrate
624
in FIG.
6
E. These gates
530
are connected to the decoder input B and the transistors are shorted because there is a doped layer
526
in the channel node
320
. In this manner, the transistors are conducted and are not controlled by the decoder input B. Because the DAC
108
(n) includes P-type DAC unit
202
and N-type DAC unit
204
, it is necessary to form the P-type doped layer and N-type doped layer independently with two additional masks.
FIG. 7
shows the layout of the decoder
302
in
FIG. 3
according to another conventional method. Th

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