Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Patent
1996-12-20
1998-01-13
Fahmy, Wael
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
257706, 257522, 257778, H01L 23367
Patent
active
057082839
ABSTRACT:
A high power, flip-chip microwave monolithic integrated circuit (MMIC) assembly (30) has a high power microwave monolithic integrated circuit (MMIC) having a surface with an active area (72) in which heat is generated. The assembly also has a host substrate (34). A thermally conductive bump (51) formed over the surface of the MMIC has a first portion (51') in close proximity to and in thermal communication with the active area (72) of the MMIC and a second portion (51") which is in close proximity to and in thermal communication with the host substrate (34). The second portion (51") of the thermal bump (51) has a greater cross-sectional area than the first portion (51'). A multi-layer, multi-exposure method of manufacturing the improved thermal bump (51) includes several steps. A plating membrane (80) is formed on a surface of the MMIC (32). A first layer of negative photoresist is applied to the surface of the plating membrane (80), and is exposed with a first masked pattern of light. A second layer of negative photoresist is applied on top of the first layer of photoresist. The second layer of negative photoresist is exposed with a second masked pattern of light. Unexposed areas of the first and second layers of photoresist form a "T" shape. The first and second layers of photoresist are developed with a photoresist developer, thereby leaving a "T"-shaped via in the photoresist. An electrically and thermally conductive metal is plated onto the plating membrane and into the via to form a substantially "T"-shaped bump (51), which is then attached to a host substrate. The resulting bump has greater cross-sectional area at the host substrate than at the MMIC (32).
REFERENCES:
patent: 4845542 (1989-07-01), Bezuk et al.
patent: 4912545 (1990-03-01), Go
patent: 4917466 (1990-04-01), Nakamura et al.
patent: 4959705 (1990-09-01), Lemnios et al.
patent: 5168329 (1992-12-01), Shiga
patent: 5319237 (1994-06-01), Legros
patent: 5345106 (1994-09-01), Doering et al.
patent: 5349239 (1994-09-01), Sato
patent: 5350947 (1994-09-01), Takekawa et al.
patent: 5352926 (1994-10-01), Andrews
patent: 5376584 (1994-12-01), Agarwala
patent: 5424693 (1995-06-01), Lin
patent: 5506755 (1996-04-01), Miyagi et al.
IBM Technical Disclosure Bulletin, vol. 35, No. 3, Aug. 1992, New York, pp. 29-30.
Patent Abstracts of Japan, vol. 015, No. 465 (E-1138), Nov. 26, 1991 & JP-A-03 201701, 3 Sep. 1991.
IBM Technical Disclosure Bulletin (vol. 13, No. 2, Jul. 1970) p. 510.
Gray William D.
Wen Cheng P.
Wong Wah S.
Denson-Low W. K.
Fahmy Wael
Hardy David B.
Hughes Aircraft
Lachman M. E.
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