Silicon-based inductor with varying metal-to-metal conductor...

Details Silicon-based inductor with varying metal-to-metal conductor... Silicon-based inductor with varying metal-to-metal conductor...

2002-05-10

2004-03-30

Mai, Anh (Department: 2832)

Inductor devices

Coil or coil turn supports or spacers

Printed circuit-type coil

C336S223000, C336S232000

Reexamination Certificate

active

06714112

ABSTRACT:

FIELD OF THE INVENTION
The present claimed invention relates to the field of semiconductor processing. More particularly, the present claimed invention relates to a novel on-chip inductor with varying spacing between the turns of the inductor to optimize inductor performance by reducing substrate as well as conductor eddy current.
BACKGROUND ART
Increasing demands for personal mobile communication equipment have motivated recent research activities to focus on the development of inexpensive, small size, low power consumption, and low noise level systems. Advances in technology are making it possible to develop radio frequency (RF) circuits on a single silicon chip. Silicon, with its mature technology, low fabrication cost as well as high packing density is recognized as the only material able to satisfy the needs of a rapidly growing communication market. To fulfill all the above-mentioned requirements, one of the most important and indispensable circuit components is the on-chip silicon-based spiral inductor.
Nevertheless, difficulties of realizing high quality factor (Q) inductors pose a great challenge for silicon radio frequency integrated circuit (IC) applications. One difficulty in achieving such high-Q inductors is dealing with substrate losses. Several fabricating techniques, methods and processes have been proposed to improve the performance of silicon-based on-chip inductors because of their high substrate losses compared to the lossless substrate used in monolithic microwave integrated circuit (MMIC) technology (see e.g., U.S. Pat. No. 5,884,990 to Joachim N. Burghartz et al., entitled “Integrated Circuit Inductor”, issued Mar. 23, 1999; N. Camilleri, D. Lovelace, J. Costa and N. David, “New Development Trends for Silicon RF Device Technologies”, IEEE Electron Device Letters, Vol. 17, No. 9, pp. 428-430, September 1996; John R. Long and Miles A. Copeland, “The Modeling, Characterization and Design of Monolithic Inductors for Silicon RF ICs”, IEEE Journal of Solid-State Circuits, Vol. 32, No. 3, pp. 357-368, March 1997; and Joachim N. Burghartz, A. E. Ruehli, M Soyuer, D. Nguyen Ngoc, and Keith A. Jenkins, “Novel Substrate Contact Structure for High-Q Silicon Integrated Spiral Inductors,” Tech. Dig. Int. Electron Devices Meeting (IEDM), pp. 55-58, 1997).
Tedious processes such as etching away the silicon substrate underneath the inductors have been introduced to remove the substrate effects. While this may achieve good results, this processing technique raises reliability issues like packaging yield and long-term mechanical stability.
Since the conductive substrate contributes significantly to capacitive and magnetic loss for inductors on silicon, another common approach is to increase the substrate resistivity (see e.g., U.S. Pat. No. 5,884,990). This method seems promising but the option is uncommon for current CMOS technology because latch-up immunity for a highly conductive substrate has to be maintained at tighter design rules.
Another barrier for obtaining a high inductance (L) value is the typical usage of aluminum-copper (AlCu) interconnects in the silicon process. Alternatively, in the GaAs technology, thicker and less resistive gold (Au) metalization together with lossless substrate may permit a high performance inductor to be fabricated. However, this may come at added expense.
Other possible alternatives include employing an active inductor, whereby its electrical properties are described through an active circuitry. In an active inductor, high Q-factor and inductance can be achieved in a relatively small silicon area. But this approach suffers from high power consumption and high noise levels, which are not acceptable for low power and high frequency applications. In addition, the performance of active inductors is very sensitive and dependent on their biasing circuitry, making them time consuming and difficult to design.
With current processes and material limitations in the existing mature silicon technology as well as stringent circuit specifications, the conventional spiral inductor remains the simplest and most effective on-chip inductor.
FIG.
1
A and
FIG. 1B
illustrate the formation of induced eddy current
108
in the substrate
104
and its magnetic flux interaction with that of the inductor. Referring to FIG.
1
A and
FIG. 1B
, in the conventional spiral inductor
102
design, the inductor
102
is planar and fabricated on a highly conductive silicon substrate
104
. Magnetic loss occurs when inductors
102
are built on such substrates
104
. The inductor
102
is shown with its inductor current
110
traversing the spiral and with its associated magnetic field
112
(H
Inductor
) Currents are shown with an “x” going into the Figures and a “point” coming out of the Figures, in the conventional manner.
According to Faraday's law, an image (or eddy) current
108
is induced in the substrate
104
underneath the spiral inductor
102
. Since the silicon substrate
104
has low resistivity, this image current
108
can flow easily. In compliance with Lenz's law, the direction of flow for this induced current
108
is opposite to that of the inductor's current
110
. This generates a parasitic magnetic field (H
Substrate
)
106
in the substrate
104
, which opposes the magnetic field
112
(H
Inductor
)of the inductor
102
. This results in a degradation of the inductor's overall useful inductance.
FIG. 1
also shows the inductor's underpass
111
connected to the spiral by vias
113
. Arrows are used to show the direction of magnetic fields. Also shown are a field oxide layer
130
, a spiral arm inter-metal dielectric layer
150
, and an inductor underpass inter-metal dielectric layer
140
.
Other than substrate eddy currents
108
, effects of conductor eddy currents generated in the inner turns of spiral inductors must not be neglected.
FIG. 2
illustrates the formation of these conductor eddy currents
208
(I
Eddy
), as well as a conductor eddy magnetic flux B
Eddy
206
. The circular inductor
102
carries a current I
Spiral
110
which flows in the direction as indicated. This current
110
generates an associated magnetic flux B
Spiral
112
, which has a maximum intensity at the center of the spiral
102
. For the case of a huge inductor
102
with several turns
220
, a large part of this magnetic flux
112
does not pass through the center of the spiral
102
but rather through its inner turns
220
. Due to a time varying nature of the coil current, the generated magnetic flux B
Spiral
112
, also varies with time. In accordance to Faraday and Lenz's laws, an electric field is magnetically induced in these inner turns
220
, generating circular eddy currents I
Eddy
208
which flow in the direction opposing the original change in magnetic flux
112
. The magnitude of this induced electrical field is proportional to the derivative of B(t) with respect to time suggesting this effect to be very significant at high frequencies.
The eddy currents
208
will cause a non-uniform inductor spiral current flow
110
in the inner turns
220
of the spiral
102
. On the inner side of the inner turns
220
, the inductor current
110
(I
Spiral
) and eddy current
208
(I
Eddy
) flow in the same direction. The outer side of the inner turn
220
, however, has a very low current density because these two currents (
110
,
208
) are in the opposite direction. In some cases, the magnitude of the eddy current
208
can be larger than the spiral current
110
. Therefore, the resultant coil current (not shown) in the inductor's inner turns
220
will flow in the “wrong” direction. This drastically reduces the overall inductance as well as quality factor of the inductor
102
.
As yet another concern, in order to achieve widespread acceptance, and to ensure affordability, any method of forming an on-chip silicon-based inductor, which overcomes the above-listed drawbacks, should be compatible with existing semiconductor fabrication processes.
Thus, a need exists for an on-chip silicon-based inductor. A further need exists

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