Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific voltage responsive fault sensor
Reexamination Certificate
2001-04-12
2004-02-24
Vu, Bao Q. (Department: 2838)
Electricity: electrical systems and devices
Safety and protection of systems and devices
With specific voltage responsive fault sensor
C361S091300, C361S093100
Reexamination Certificate
active
06697241
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of protection circuits for rechargeable battery cells. More specifically, the present invention relates to the field of protection circuits that address inductive flyback when current flow is interrupted to a load through the metal oxide semiconductor field effect transistor (MOSFET) switch.
2. Related Art
Rechargeable battery packs require a means for limiting the discharge current when an excessive load is applied to the pack's terminals. For example, a protection circuit will protect against an effective short circuit of the battery. Typically, a series MOSFET switch and a protection circuit that monitors the state of the discharge current is used for this function. However, a problem exists in this standard approach in that high voltage due to parasitic inductance will damage the protection circuit.
FIG. 1
of the prior art shows a circuit
100
with a p-channel MOSFET (PMOS) switch protection circuit
110
as represented within the dotted lines. A parasitic lead inductance originates from a parasitic inductor
120
that is in series between the rechargeable battery cell
130
and the protection circuit
110
.
A PMOS
115
either conducts or is turned-off depending on the state of the switch
117
. A overcurrent sensor (not shown) senses the current flowing through the protection circuit and through system
100
. When the system
100
is in a normal operation, the switch
117
is set to ground allowing the PMOS
115
to conduct. When the overcurrent sensor senses that an extremely high current load is applied to the protection circuit and the system
100
, the switch
117
is thrown to the right tying the source and the gate of the PMOS
115
together. This, in turn, puts PMOS
115
into a non-conducting state since V
GS
is zero.
FIG. 1
of the prior art depicts a nominal value current (I
loadDC
) flowing from the battery cell
130
, through the inductor
120
and the conducting PMOS switch into a nominal load.
A typical situation where an effective short is placed across the battery cell
130
is also shown in FIG.
1
. At time t=0, a very high current load is applied, such as when a capacitor
150
with a charge of zero volts is put onto the circuit. As discussed previously, the sensing circuit (not shown) will throw the switch
117
to the right in order to put the PMOS
115
into a non-conductive state in order to protect the battery cell
130
from a short circuit.
The application of this load forces the voltages at both V
B
, at node
113
, and V
A
, at node
119
, to drop. The voltage at V
A
is set by the resistor divider formed by the on-resistance of the MOSFET switch and the effective series resistance (ESR) of the battery.
This resulting instantaneous interruption of cell current causes the voltage across the parasitic inductor to rapidly increase with a reverse potential. In other words, the inductance through the parasitic inductor is great enough to establish many volts of flyback through the inductor. Since there is no significant impedance from the source or gate of the PMOS to ground, the voltage at V
A
is effectively unbounded except by flyback voltage.
Thus, the magnitude of voltage increase at V
A
is often enough to exceed the absolute maximum voltage rating of the protection circuit's IC process. This can damage circuitry by either breaking down junctions or oxides. This scenario occurs in circuits with both practical component values and with practical protection circuit response times.
SUMMARY OF THE INVENTION
Accordingly, a circuit for preventing high voltage damage to a metal oxide semiconductor field effect transistor (MOSFET) switch in series with an inductor and a rechargeable battery source is described. The present invention provides for a circuit that addresses the high voltages resulting from inductive flyback when current flow is interrupted through the protection circuit.
Specifically, in one embodiment of the present invention, the present invention discloses a protection circuit comprising a transistor and a clamp circuit. The transistor is coupled in series to a load, an inductor, and a rechargeable battery cell. The clamp circuit temporarily turns-on the transistor when the transistor has been turned-off by a switch and the gate and source voltage rises. The clamp circuit is coupled to the gate of the transistor.
The transistor, in one embodiment, is a p-channel MOSFET (PMOS) field effect transistor. The PMOS includes a source terminal that is coupled in series with the inductor and to a positive terminal of said battery cell. The PMOS also includes a drain terminal coupled to the load.
The protection circuit also includes a switch for turning-off the transistor when a high current overload is detected in the protection circuit. The switch couples the PMOS gate to the PMOS source when the switch turns-off the transistor.
The clamp circuit temporarily allows for the transistor that has been turned-off to conduct when a positive rate change of voltage with respect to time occurs at the PMOS gate.
In one embodiment of the present invention, the clamp circuit is a differentiator circuit with an RC time constant. The differentiator circuit is comprised of a capacitor, a pull-down resistor, and an n-channel MOSFET (NMOS).
Specifically, another embodiment of the present invention discloses a protection circuit comprising a PMOS coupled in series to a load, an inductor, and a rechargeable battery cell. The PMOS is switched to a non-conductive state by a switch in order to prevent overloading the protection circuit. A clamp circuit temporarily allows the PMOS to conduct when a positive rate change of voltage with respect to time occurs at the gate of the PMOS. The clamp circuit is coupled to the gate of the PMOS. The clamp circuit has an RC time constant and is comprised of an NMOS, a capacitor, and a pull-down resistor.
REFERENCES:
patent: 5684663 (1997-11-01), Mitter
patent: 6043965 (2000-03-01), Hazelton et al.
patent: 6185082 (2001-02-01), Yang
patent: 6201677 (2001-03-01), Sakamoto et al.
patent: 6385025 (2002-05-01), Sakamoto et al.
patent: 6385028 (2002-05-01), Kouno
patent: 6430016 (2002-08-01), Marr
National Semiconductor Corporation
Vu Bao Q.
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