Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-02-26
2004-03-09
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S778000, C438S791000, C438S296000
Reexamination Certificate
active
06703287
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method of producing a semiconductor device, and more specifically to an improved method of producing a semiconductor device in which overpolishing at a chemical mechanical polishing time is prevented to eliminate the influence of peripheries on the object part. The present invention is also related to a semiconductor device produced by such a method.
2. Description of the Background Art
In the following description, an alignment mark of a stepper is used as an example of a photo-related mark.
FIG. 14
is a cross-sectional view of a densely aggregated pattern (object part)
9
and a chip periphery part (including a dicing part)
8
.
Referring to
FIG. 14
, an oxide film
2
and a nitride film
3
are successively formed on a silicon substrate
1
. By a conventional photolithography and etching technique, an isolation part
6
and a photo-related mark part
4
are formed. Referring to
FIG. 15
, a high-density plasma oxide film
10
is buried in the isolation part
6
and the photo-related mark part
4
. This forms an isolation region. According as the size reduction proceeds, the active region will become smaller due to a bird's beak by the LOCOS technique, so that such an isolation technique is used.
At this time, referring to
FIG. 15
, the high-density plasma oxide film
10
is formed on the isolation part
6
, the photo-related mark part
4
and the nitride film
3
, since the high-density plasma oxide film
10
is deposited while maintaining anisotropy. A step difference corresponding to the height of the high-density plasma oxide film
10
formed on the nitride film
3
is generated on the silicon substrate
1
. Also, since the active region is small in the densely aggregated pattern (object part)
9
, the high-density plasma oxide film
10
is deposited successively from the isolation part
6
, and intersects at a central part of the active region. Therefore, as shown in the drawings, the high-density plasma oxide film
10
has a cross section shape like a mountain in the densely aggregated pattern part
9
to form a ridge. The height of the high-density plasma oxide film
10
formed on the active region will be smaller than the thickness of the high-density plasma oxide film
10
formed on the chip peripheral part
8
. For this reason, there will be a step difference between a coarse pattern such as the chip peripheral part (including the dicing part)
8
and the densely aggregated pattern (object part)
9
.
FIG. 20
is a plan view of the semiconductor device shown in FIG.
15
. Namely,
FIG. 15
is a cross-sectional view along the line X
1
-X
2
of FIG.
20
.
In order not to leave the aforesaid step difference to the later steps, the surface of the silicon substrate
1
is polished by chemical mechanical polishing technique (hereafter referred to as CMP); however, even if it is directly subjected to CMP, the high-density plasma oxide film
10
will remain or the CMP does not stop at the surface of the nitride film and causes overpolishing, since the step difference is too large.
Therefore, in the conventional technique, a resist film
11
is formed on the isolation part
6
, as shown in FIG.
16
. Next, referring to
FIGS. 16 and 17
, the high-density plasma oxide film
10
is removed by etching with the use of the resist film
11
as a mask. Hereafter, such removal of a large high-density plasma oxide film
10
on the active region in advance before CMP polishing, will be referred to as pre-etching.
In order to define the size of the active region where the pre-etching is to be performed, a superposition shift at the time of photolithography for pre-etching and the margin of the variation of the resist dimension will be required, Since the high-density plasma oxide film
10
is deposited obliquely at pattern edges, the oblique portion will be 0.4 to 0.5 &mgr;m if the deposited amount is 0.4 to 0.5 &mgr;m, thereby requiring a margin of 0.4 to 0.5 &mgr;m on one side.
Though it depends on the conforming degree of the pre-etching photolithography to the size reduction, the active region that can be pre-etched must have a pattern with a size larger than 1.0 to 2.0 &mgr;m. Therefore, it is not possible to pre-etch a fine pattern having an active region smaller than 1.0 &mgr;m, such as a memory device cell. Concerning the photo-related mark part
4
, the buried high-density plasma oxide film
10
is etched at the pre-etching time, as shown in FIG.
17
. This is due to the following reason. In superposition of a transfer gate (TG) and a later-step layer, if a metal-series material is used in the superposed layer, the precision drops if there is no step difference (if it is directly subjected to CMP, it is planarized to remove the step difference) between the superposed layer and the foundation layer (FL).
Even if the high-density plasma oxide film
10
of the photo-related mark part
4
is not etched at the pre-etching time, a step (photolithography, etching) of removing the high-density plasma oxide film
10
of the photo-related mark part
4
is needed somewhere for superposition with the layer in a later step. Therefore, in a prior art technique, the high-density plasma oxide film
10
of the photo-related mark part
4
is etched at the pre-etching time for step reduction (cost reduction).
FIG. 21
corresponds to a plan view of the device shown in FIG.
17
. Namely,
FIG. 17
is a cross-sectional view along the line X
1
-X
2
of FIG.
21
.
Referring to
FIG. 21
, the high-density plasma oxide film
10
is removed by etching at the photo-related mark part
4
.
Referring to
FIG. 18
, a surface of the silicon substrate
1
is polished by CMP. This removes the high-density plasma oxide film
10
on the nitride film
3
. At this time, in the prior art technique, there is a step difference generated at the photo-related mark part
4
, and the polishing pressure
13
of CMP is applied thereon to a greater extent than on the other parts, and also slurries caused by chemical polishing are liable to be deposited at the step difference part.
Therefore, at the step difference of the photo-related mark part
4
, chemical polishing also proceeds to a greater extent than at the other parts. Also, since the high-density plasma oxide film
10
to be removed by CMP is absent, the nitride film
3
is directly polished at the CMP time, whereby the nitride film
3
is also liable to be shaven. Therefore, if the CMP polishing is carried out to such an extent as to remove the high-density plasma oxide film
10
which is on the nitride film
3
of the densely aggregated pattern
9
, overpolishing
14
occurs at and near the center of the photo-related mark part
4
. If excessive overpolishing
14
occurs, the region of the densely aggregated pattern
9
will also be overpolished.
Thereafter, referring to
FIG. 19
, when the nitride film
3
and the pad oxide film
2
are removed by a conventional technique, substrate shaving
15
occurs at the part shown by A in
FIG. 19
or the high-density plasma oxide film
10
at the pattern edge drops down to a position below the surface of the silicon substrate
1
.
FIG. 22
is a plan view of the device shown in FIG.
19
. Namely,
FIG. 19
is a cross-sectional view along the line X
1
-X
2
of FIG.
22
.
FIG. 23
is a view illustrating a configuration of the photo-related mark part
4
in a conventional object part chip. If a plurality of such photo-related mark parts
4
are aggregated, the polishing pressure at the CMP time is further concentrated to increase the substrate shaving
15
or dropping that starts at that part. As the photo-related mark, there are a global mark used for superposition of a stepper or the like, an LSA mark and an FIA mark used for fine alignment, a mark used for the inspection of superposition, a vernier for eye inspection of photographs, and others. Even with the same mark, if the layers to be superposed are different, the same mark is needed for the number of the layers.
The substrate shaving causes substrate leakage or d
Fujiishi Yoshitaka
Ueno Atsushi
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Pham Long
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