Voltage down converter

Details Voltage down converter Voltage down converter

2002-11-22

2004-10-19

Patel, Rajnikant B (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S282000

Reexamination Certificate

active

06806692

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to a voltage down converter and more particularly, to an improved voltage down converter that provides a supply voltage and current to a device, and that utilizes a pair of circuits to supply steady state current and fluctuating current to the device with minimal voltage variation and improved stability relative to prior voltage down converters.
BACKGROUND OF THE INVENTION
Voltage down converters or “VDCs” are used to lower the level of an external power supply voltage (e.g., Vcc) provided to a semiconductor device to a desired internal power supply voltage (e.g., Vdd). For example, in a semiconductor device, a voltage down converter may lower an external power supply voltage to the level of an internal power supply voltage, so that each component element within the device may be operated with the internal power supply voltage to secure sufficient reliability of each component element.
FIGS. 1A-C
illustrate a conventional voltage down converter (“VDC”) in accordance with the prior art. In existing chip designs, a VDC may be used in various applications to supply large amount of “AC” type current (e.g., alternating or fluctuating current) while concomitantly sustaining necessary “DC” type current (e.g.; a fixed current) and a steady DC voltage level. Examples of semiconductor devices that utilize VDCs are SRAM and DRAM devices. The conventional VDC design has some drawbacks when employed in modern applications, which often require large, fluctuating output currents. To provide a large current, the VDC will typically require a relatively large source follower transistor P
1
, as shown in FIG.
1
C. In order to drive the large transistor P
1
, the comparator C has to be relatively powerful. The relatively large transistor and comparator size results in substantial and undesirable current consumption for the VDC. Also, the feedback or coupling capacitor, Pcc, has to be relatively large in size to stabilize the VDC. The voltage divider formed by resistors R
1
, R
2
is used to provide a desired device or supply voltage (Vdd). In the embodiment of
FIGS. 1A-C
, the values of the resistors R
1
and R
2
, the device voltage, Vdd, reference voltage, Vref, and feedback loop voltage, Vfb, are related as follows:
Vref=Vfb+Voffset
(where
Voffset
is the input offset voltage of the OPAMP)
Vfb
=(
Vdd*R
2)/(
R
1
+R
2)
Vdd
=(
Vref−Voffset
)*(
R
1
+R
2)/
R
2
The power to performance ratio of this type of prior VDC diminishes with increasing current supply requirements. In the presence of increasing current demands, the conventional VDC eventually becomes sluggish to supply adequate AC current for digital circuits. When such a scenario occurs, the VDC cannot maintain the output voltage Vdd at a steady level and voltage level dipping occurs. In an SRAM or a DRAM chip, a large dip in voltage level can cause memory cells to fail.
There is therefore a need for a new and improved voltage down converter for use with semiconductor devices, which can provide relatively large output currents and voltages, which minimizes voltage variations during operation, and which has improved stability and robustness.
SUMMARY OF THE INVENTION
One non-limiting advantage of the invention is that it provides an improved voltage down converter for use with semiconductor devices, such as SRAM and DRAM devices.
Another non-limiting advantage of the invention is that it provides a voltage down converter that utilizes a “DC” circuit portion that provides a relatively large steady state output current, and an “AC” circuit portion that provides and controls relatively small output current fluctuations. The AC and DC circuit portions cooperate to provide the desired supply voltage and current with minimal voltage variations and improved stability.
Another non-limiting advantage of the invention is that it provides a voltage down converter that utilizes a pair of comparators that collectively consume less power than single comparator designs of the prior art.
Another non-limiting advantage of the invention is that it provides a voltage down converter that can operate under increasing current demands, while minimizing supply voltage variation and having improved stability and robustness.
According to a first aspect of the present invention, a voltage down converter is disclosed for providing a supply voltage and current to a device. The voltage down converter includes a first circuit portion for providing a first current for supplying steady state current to the device; a second circuit portion for providing a second current for supplying fluctuating current to the device; and a third circuit portion for controlling a value of the supply voltage at an output node.
According to a second aspect of the present invention, a circuit for providing a supply voltage and current to a device is disclosed. The circuit includes a first circuit for supplying steady state current to the device, the first circuit including a first comparator having a first output node and a first transistor having a gate coupled to the first output node, thereby allowing the first comparator to drive the first transistor to supply the first current. A second circuit provides fluctuating current to the device, the second circuit including a second comparator, which is larger than the first comparator and which has a second output node, and a second transistor having a gate coupled to the second output node, thereby allowing the second comparator to drive the second transistor to supply the fluctuating current. Finally, a third circuit provides a feedback signal to the first and second comparators for controlling a value the supply voltage.
According to a third aspect of the present invention, a method of providing a supply voltage and current to a device is disclosed. The method includes the steps of: providing a first current for supplying steady state current demands of the device; providing a second current for supplying fluctuating current demands of the device; and controlling a value of the supply voltage at an output node.
These and other features, advantages, and objects of the invention will become apparent by reference to the following specification and by reference to the following drawings.


REFERENCES:
patent: 4395675 (1983-07-01), Toumani
patent: 5959442 (1999-09-01), Hallberg et al.
patent: 6680656 (2004-01-01), Chen
Gerrit W. Den Besten, et al.; Embedded 5 V-to-3.3 V Voltage Regulator for Supplying Digital IC's in 3.3 V CMOS Technology, IEEE Journal of Solid-State Circuits, vol. 33, No. 7, Jul. 1998; pp. 956-962.
Tsukasa Ooishi, et al.; A Mixed-Mode Voltage Down Converter with Impedance Adjustment Circuitry for Low-Voltage High-Frequency Memories; IEEE Journal of Solid-State Circuits, vol. 31, No. 4, Apr. 1996, pp. 575-585.
Robert J. Widlar; New Developments in IC Voltage Regulators; IEEE Journal of Solid-State Circuits, vol. SC-6, No. 1, Feb. 1971; pp. 2-7.

Affiliated with

Also associated with

Rating

Voltage down converter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Voltage down converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Voltage down converter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3287966