Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – Avalanche diode
Reexamination Certificate
2002-02-22
2004-02-03
Wille, Douglas A. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
Avalanche diode
C257S355000
Reexamination Certificate
active
06686641
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a semiconductor device used for a semiconductor integrated circuit, and more particularly relates to a constant voltage device used as a semiconductor internal voltage booster, for example.
A constant voltage device called “clamping diode” has heretofore been used to fix a voltage, which has been increased by a semiconductor internal voltage booster, at a desired constant voltage. Such a clamping diode is also termed “zener diode”, which is used for obtaining a desired constant voltage by utilizing a reverse breakdown phenomenon at a pn junction between a semiconductor substrate and a doped layer formed on the semiconductor substrate. Hereinafter, an exemplary conventional constant voltage device of this type will be described.
FIG. 10
is a cross-sectional view illustrating an exemplary structure of a conventional semiconductor device functioning as a constant voltage device. As shown in
FIG. 10
, a field oxide
2
is formed on a P-type semiconductor substrate
1
so as to surround and define an active region
3
. A P-type doped layer
4
is formed as a channel stopper just under the field oxide
2
, and an N-type doped layer
5
is formed in the active region
3
. An interlevel dielectric film
6
is formed over the substrate. And the N-type doped layer
5
is connected to an aluminum interconnect
7
through an opening of the interlevel dielectric film
6
.
In this case, the constant voltage device is configured in such a manner that the desired constant voltage thereof is determined by a reverse breakdown voltage of the pn junction between the N-type and P-type doped layers
5
and
4
. Specifically, when a reverse voltage, exceeding the constant voltage, is applied to the region between the aluminum interconnect
7
and the P-type semiconductor substrate
1
,′ reverse current flows between the N-type and P-type doped layers
5
and
4
due to the zener effect or avalanche effect. Based on this principle, even if a high voltage is applied, the voltage between the aluminum interconnect
7
and the P-type semiconductor substrate
1
is substantially fixed at a constant voltage.
The conventional configuration, however, has the following problems.
When the reverse breakdown phenomenon happens at the pn junction between the N-type and P-type doped layers
5
and
4
, electron-hole pairs are created. And, as shown in
FIG. 11
, holes, for example, of the electron-hole pairs are trapped in the vicinity of the interface between the field oxide
2
and the P-type doped layer
4
around the periphery of the active region
3
. As a result, the strength of the electric field in the direction originating from the N-type doped layer
5
toward the P-type doped layer
4
in the pn junction plane is weakened by the electric field exerted by the holes trapped. Thus, supposing the potential in the P-type semiconductor substrate
1
is constant, a higher voltage should be applied between the N-type doped layer
5
(or the aluminum interconnect
7
) and the substrate
1
to increase the voltage between the P-type and N-type doped layers
4
and
5
up to the reverse breakdown voltage at the pn junction. Hereinafter, such a voltage between the N-type doped layer
5
(or the aluminum interconnect
7
) and the substrate
1
, required to cause the breakdown of the pn junction, will be referred to as a “reverse withstand voltage” Also, as the quantity of charges flowing from the N-type doped layer
5
into the P-type doped layer
4
increases, the total quantity of holes trapped also increases. Thus, the reverse withstand voltage further increases with the passage of time, i.e., varies as represented by the plot identified with X in FIG.
4
. It should be noted that electrons might be possibly trapped in the vicinity of the interface between the field oxide
2
and the P-type doped layer
4
depending on the specific structure of the semiconductor device. In such a case, the reverse withstand voltage continuously decreases with time.
That is to say, the overall performance of the semiconductor device as a constant voltage device deteriorates with time, because the reverse withstand voltage is variable from the desired constant voltage.
SUMMARY OF THE INVENTION
In view of these problems, a prime object of the present invention is providing a semiconductor device as a constant voltage device that can suppress the variation in reverse withstand voltage with time by taking various measures.
A first semiconductor device according to the present invention includes: a semiconductor substrate; a semiconductor region of a first conductivity type formed in the semiconductor substrate; a doped layer of a second conductivity type formed in the semiconductor region; an isolating insulator film formed on the semiconductor substrate so as to surround the doped layer; a first electrode in contact with the doped layer; and a second electrode formed at least on the isolating insulator film and made of a conductor film in the vicinity of the doped layer.
In this structure, the quantity of carriers trapped in the interface between the isolating insulator film and the semiconductor region can be reduced by regulating the voltage applied to the second electrode. Accordingly, a semiconductor device having a function of suppressing the variation in reverse withstand voltage can be obtained.
In one embodiment of the present invention, the second electrode is preferably formed on part of the isolating insulator film, the part including at least an end of the isolating insulator film.
In another embodiment of the present invention, the isolating insulator film may be at least partially spaced apart from the doped layer with an offset region interposed therebetween, and the second electrode may overlap the isolating insulator film and the offset region.
In such an embodiment, at least part of the interface between the isolating insulator film and the semiconductor region is offset from the pn junction where electron-hole pairs are created. Accordingly, the quantity of holes or electrons trapped in the vicinity of the interface can be reduced. As a result, a semiconductor device having a superior function of suppressing the variation in reverse withstand voltage can be obtained.
In still another embodiment of the present invention, the second electrode may be connected to a ground terminal.
In an alternate embodiment, the second electrode may be connected to a power supply terminal.
In another alternate embodiment, the second electrode may be connected to the power supply terminal via a resistor.
In still another alternate embodiment, the second electrode may be connected to the doped layer.
In these embodiments, it is possible to suppress carrier trapping using a simple configuration without providing any special control function.
In still another embodiment, the semiconductor device may further include a channel stopper region formed under the isolating insulator film in the semiconductor region and heavily doped with a dopant of the first conductivity type.
In such an embodiment, a semiconductor device exhibiting smaller variation in reverse withstand voltage with time can be formed by regulating the reverse withstand voltage using the channel stopper enhancing the isolation function.
In still another embodiment, the semiconductor device may further include a reverse withstand voltage regulating region formed between the doped layer and the channel stopper region in the semiconductor region and doped with a dopant of the first conductivity type more heavily than the semiconductor region and more lightly than the channel stopper region.
In such an embodiment, the initial value of the reverse withstand voltage can be regulated, and the charge quantity per unit volume of the electron-hole pairs created and trapped can be reduced. Accordingly, it is possible to suppress the variation in reverse withstand voltage with time.
A second semiconductor device according to the present invention includes: a semiconductor substrate; a semiconductor region of
Akashi Takuo
Arai Katsujirou
Doi Hiroyuki
Honda Hirotsugu
Yoshii Naritsugu
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Studebaker Donald R.
Wille Douglas A.
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