Semiconductor device manufacturing: process – Making passive device
Reexamination Certificate
2002-08-29
2004-12-14
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Making passive device
C438S386000, C438S393000
Reexamination Certificate
active
06830983
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and, in particular, to diffusion barrier layers in dense semiconductor memory arrays.
BACKGROUND OF THE INVENTION
In the fabrication of integrated circuits, various conductive layers are used. For example, during the formation of semiconductor devices, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), ferroelectric (FE) memories, etc., conductive materials are used in the formation of storage cell capacitors and also may be used in interconnection structures, for example, conductive layers in contact holes, vias, etc. In many applications, it is preferable that the material used provides effective diffusion barrier characteristics.
For example, effective diffusion barrier characteristics are required for conductive materials used in the formation of storage cell capacitors of memory devices, such as DRAMs. As memory devices become denser, it is necessary to decrease the size of circuit components forming such devices. One way to retain storage capacity of storage cell capacitors of memory devices and at the same time decrease the memory device size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. Therefore, high dielectric constant materials are used in such applications interposed between two electrodes. One or more layers of various conductive materials may be used as the electrode material. However, generally one or more of the layers of the conductive materials used for the electrodes, particularly the lower electrode of a cell capacitor, must have certain barrier properties and oxidation resistance properties. Such properties are particularly required when high dielectric constant materials are used for the dielectric layer of the storage cell capacitor because of the processes used for forming such high dielectric materials. For example, deposition of high dielectric materials can occur at temperatures greater than 450° C., in an oxygen-containing atmosphere or involves post deposition anneals in excess of 700° C. in an oxidizing atmosphere.
Generally, various metals and metallic compounds, and typically noble metals, such as platinum, have been proposed as the electrodes or at least one of the layers of electrodes for use with high dielectric constant materials as insulators for high dielectric MIM (metal-insulator-metal) storage cell capacitors. However, reliable electrical connections should generally be constructed which do not diminish the beneficial properties of the high dielectric constant materials. For platinum to function well as a bottom electrode, it must be an effective barrier to the diffusion of oxygen and silicon. This is required since any oxidation of the underlying silicon upon which the capacitor is formed will result in decreased series capacitance thus degrading the storage capacity of the cell capacitor. Platinum, used alone as an electrode layer, is too permeable to oxygen to be used as a bottom electrode of a storage cell capacitor.
Various high dielectric materials are used as insulators in MIM capacitors. For example, dielectric materials include tantalum oxide (Ta
2
O
5
), strontium titanate (SrTiO
3
), alumina (Al
2
O
3
), barium strontium titanate BaSrTiO
3
(BST) zirconium oxide (ZrO
2
), and hafnium oxide (HfO
2
). Generally, such high dielectric materials are deposited at temperatures higher than 450° C., in an oxygen-containing atmosphere or are annealed in oxygen-containing atmosphere to further oxidize and improve the dielectric properties, such as the dielectric constant and leakage of the dielectric materials. Generally, the dielectric properties of these dielectric materials improve with increased temperatures of deposition and/or anneal. Current barrier materials are only able to provide an effective barrier against diffusion of oxygen into the underlying silicon layer during deposition and oxidation of the high dielectric materials up to a temperature of around 650° C. Since platinum is very permeable to oxygen, without an effective barrier layer between the platinum and the underlying silicon, the oxygen will diffuse through the platinum during oxidation of the dielectric materials at temperatures higher than 450° C.
In addition, in some embodiments, semiconductor structures include a polysilicon contact to provide electrical communication between the substrate and the platinum bottom electrode of the MIM storage cell capacitor. Further in these structures, various barrier layers are formed over the polysilicon contact and below the platinum bottom electrode. For example, such barrier layers may be titanium nitride, tungsten nitride, or any other metal nitride, which acts as a silicon barrier between contact and electrode. In addition, one or more other barrier layers may be included to prevent diffusion of oxygen for example, during deposition of high dielectric materials at high temperatures higher than 500° C. or after anneal, in an oxygen-containing atmosphere. Such barriers can also get oxidized when the temperature during deposition or anneal and oxidation of high dielectric materials is around 650° C. or higher. This can result in degrading the barrier properties. For example, a titanium nitride (TiN) barrier layer may get converted to titanium dioxide (TiO
2
) and so on.
Thus, there is a need in the art for an effective oxygen barrier layer in semiconductor structures including high dielectric MIM capacitors that can overcome the above-described problems.
SUMMARY OF THE INVENTION
The present invention provides techniques for fabricating an effective oxygen barrier layer in dense semiconductor memory arrays.
In one aspect, the invention provides methods for forming a high dielectric MIM storage cell capacitor on a silicon substrate. In one embodiment of the methods, the high dielectric MIM storage cell capacitor is fabricated by forming a barrier layer, including platinum stuffed with silicon oxide over the silicon substrate. A bottom electrode layer is then formed by using platinum over the formed barrier layer. Further, a tantalum oxide insulator layer is formed over the formed platinum layer. A top electrode layer is then formed over the formed tantalum oxide layer.
In another aspect, the invention provides methods for forming a semiconductor structure including at least one transistor device, on a silicon substrate. In one embodiment of the methods a polysilicon contact is then formed to electrically connect the formed bottom electrode layer in the container with the at least one transistor device. A titanium nitride barrier layer is then formed over the polysilicon contact. An oxygen barrier layer, including platinum stuffed with silicon oxide is then formed over the titanium nitride layer and below the bottom electrode layer. A bottom electrode layer is then formed by using platinum over interior surfaces of a container formed relative to the at least one transistor device in the silicon substrate. Further, a high dielectric insulator layer is formed over the bottom electrode layer. In addition, a top electrode layer is over the formed high dielectric insulator layer.
In another aspect, the invention provides a high dielectric MIM storage cell capacitor. In one embodiment, the high dielectric MIM storage cell capacitor includes an oxygen barrier layer, including platinum stuffed with silicon oxide, overlying a silicon substrate. A bottom platinum electrode layer overlies the oxygen barrier layer. A high dielectric layer overlies the bottom platinum electrode layer. Further, a top electrode overlies the high dielectric layer.
In yet another aspect, the invention provides a semiconductor structure including a high dielectric MIM container capacitor and at least one associated transistor device on a silicon substrate. In one embodiment, the semiconductor structure includes a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed in the silicon substrate. A high dielectric layer overlies the interior surface of
Cuneo Kamand
Geyer Scott B.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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