Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2003-04-17
2004-02-24
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S213000, C345S214000, C345S010000, C345S027000, C345S111000, C345S182000
Reexamination Certificate
active
06697058
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a device and a method for repeatedly updating the function of a liquid quid crystal (LCD) monitor, and more particularly to a device and a method for repeatedly updating the function of a LCD monitor by using Display Data Channel (DDC) signal lines for signal transmission.
2. Description of the Related Art
In a current monitor system, particularly to a LCD monitor, a monitor controller must be exchanged when function modifying or debugging, resulting in high cost consumed. As to a further advanced monitor system, a corresponding monitor controller has a build-in read only memory (ROM) which is an erasable programmable read only memory. By updating data stored in the erasable programmable read only memory, function modification and debugging can be achieved.
Referring to
FIG. 1
, a conventional programmable LCD monitor with the circuit block diagram is shown. The conventional LCD monitor has a total of 18 VGA signal lines electrically coupled to a VGA card, which includes a vertical synchronous signal (Vsync) line, a horizontal synchronous signal (Hsync) line, a serial data (SDA) line, a serial clock (SCL) line, a ground (Gnd) line, a red (R) line, a green (G) line and a blue (B) line. During a normal operation, the LCD monitor controller
10
receives the VGA signals. The LCD monitor also coupled to a jumper
14
for connection to the flash ROM
20
or the erase/record socket
80
. The flash ROM
20
stores the data used to control the displaying function. In addition, the LCD monitor
10
also has a panel connector to connect to the LCD displaying panel (not shown). Usually, the monitor controller
10
controls the display panel (not shown) based on the VGA signals. The Hsync, Vsync, SDA, SCL and R.G.B signal lines are electrically coupled to the monitor controller
10
for driving the scan and data signals to the LCD displaying panel.
When it is necessary to modify the function of the monitor system, data stored in the flash ROM
20
needs to be updated. First, the case of the monitor must be opened. Then, the first jumper
14
is used to separate the original circuit and the rewriting pathway to the flash ROM. And then, a cable connected to the socket
80
to transmit the updated data.
FIG. 2
is a schematic view showing the connection of a conventional LCD monitor system with a memory erase/record system. After the external casing of the monitor
100
is open, a main circuit board
110
is revealed. An erase/record socket
80
and a set of VGA signal lines
18
are laid on the circuit board
110
. The first jumper
14
is found within a jumper area
22
. The memory erase/record system
90
includes a ROM writer
92
, a computer system
94
and a programming monitor
96
. The computer system
94
controls all the operations of the ROM writer
92
. Programming status of the operation can be observed through the programming monitor
96
. When the ROM writer is plugged into the erase/record socket
80
of the main circuit board
110
, memory inside the monitor can be reprogrammed by the computer
94
so that a different monitor function can be used.
Obviously, it is really inconvenient to update the monitor system because the case of the conventional monitor must be first opened, and then the jumper has to be switched for recording the erasable programmable read only memory of the monitor controller
10
.
As a result, it is rather inconvenience when the monitor system, such as LCD monitor, is updated because it is necessary to open the case of the monitor and to switch jumpers for recording the erasable programmable read only memory of the monitor controller
10
.
SUMMARY OF THE INVENTION
The invention is to provides a device for reprogramming function of a LCD monitor, which needs not to open the case and needs no the conventional jumper. Also and, it is not necessary to include a connector with pre-designed layout for isolating the previously original circuit and the rewriting pathway to the flash memory. The displaying function of the LCD monitor can be repeatedly updated and the information about on-screen display.
The present invention provides a LCD monitor control system capable of reprogramming monitor function. The monitor control system utilizes the VGA signal lines for transmitting signals during normal operation. The same VGA signal lines are also used for transmitting erase/record commands to the monitor system and to erase/record data into an external erasable programmable ROM.
The invention provides a device for reprogramming function of a LCD monitor, which includes a set of video graphic adapter (VGA) signal lines for transmitting a plurality of erase/record commands and a plurality of erase/record data. A signal detector is coupled to the VGA signal lines for detecting and re-transmitting the erase/record commands and data. An activation device is coupled to the signal detector, wherein the activation device is normally connected to a video pathway, but as soon as erase/record commands are detected, the activation device is switched to an erase/record pathway so that erase/record commands and data can be re-directed. A read-only-memory (ROM) erase/record command decoder is coupled to the activation device via the erase/record pathway, wherein the decoder translates the erase/record commands into a plurality of erase/read/write signals and translates the erase/record data into a plurality of address signals and a plurality of data signals. A plurality of address signals, a plurality of data signals and a plurality of control signals are coupled to the ROM erase/record command decoder. Consequently, data stored in the external ROM unit can be modified, according to the address, data and erase/read/write signals coming from the command decoder. A mode return device is coupled to the ROM erase/record command decoder and the activation device. Wherein, the reprogramming status of the ROM unit can be determined from the address, data and read/write signals so that the activation device can be triggered to switch over connection from the erase/record pathway to the video pathway as soon as reprogramming is finished.
In the foregoing device, the signal detector further includes an inter-integrated circuit multiple address content comparator circuit, which is coupled to the VGA signal lines for comparing with a plurality of consecutive address sequences in the erase/record data such that a set signal is transmitted when there is a match with a pre-set address sequence. A monitor-in-system programming control flag unit is coupled to the inter-integrated circuit multiple address content comparator circuit for transmitting a start signal after receiving the set signal.
In the foregoing device, the activation device further includes a monitor-in-system reprogramming initialization circuit for producing a select signal after receiving the start signal, as well as an erase/record pathway isolator for switching over connection from the video pathway to the erase/record pathway after receiving the select signal and transmitting the erase/record commands and data via the erase/record pathway.
In the foregoing device, the ROM erase/record command decoder further includes an inter-integrated interface circuit for receiving and translating the erase/record commands and data, as well as an erase/record command decoder for receiving translated erase/record commands and data and outputting address, data and erase/read/write signals.
In the foregoing device, the erase/record command decoder further includes a hidden ROM for holding a program code for erase/record commands; a random access memory (RAM) unit for holding erase/record data; a central processing unit coupled to the hidden ROM, the RAM unit and the inter-integrated interface circuit. Wherein the central processing unit receives the erase/record commands and data passing through the inter-integrated circuit interface circuit and then stores the erase/record data in the RAM unit, while the erase/record commands are decoded by referring to the pr
Abdulselam Abbas
Hjerpe Richard
J.C. Patents
Novatek Microelectronics Corp.
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