Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
2000-09-19
2004-12-07
Phu, Phuong (Department: 2631)
Pulse or digital communications
Receivers
Angle modulation
C375S327000, C375S324000, C375S344000
Reexamination Certificate
active
06829311
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the demodulation of frequency modulated (FM) signals and, more specifically, it relates to a complex valued delta sigma phase locked loop (PLL) demodulator.
BACKGROUND TO THE INVENTION
Current mobile telephone handsets need to conserve as much power a possible to extend their battery life. Unfortunately, current FM demodulation techniques used in these handsets require multiple discrete components to implement. The multiplicity of these components leads to high power consumption and consequently, to shorter battery life. A single-chip demodulator would have lower power consumption and, theoretically, lead to longer battery life.
However, a single-chip demodulator is not the only requirement for the mobile handsets of the future. The demodulator must also provide some of the selectivity required in the receiver while simultaneously extracting the analogue FM information from the input IF signal. This is particularly important given the Advanced Mobile Phone System (AMPS)requirement for the demodulator to work properly with an interferer on the alternate channel only 60 kHz away from the desired signal on the assigned channel. The AMPS specification requires the receiver to continue to work properly when this interfering signal is 65 dB stronger than the desired signal.
Regarding current demodulation techniques, one of the more recently researched that of a &Dgr;&Sgr;PLL demodulator. A generalized schematic of this approach is illustrated in FIG.
1
. The principle of operation here is that the circuit is a &Dgr;&Sgr; modulator. When considered this way, the dual modulus divider (n
+d) and phase detector (PD) provide the first integrator of a &Dgr;&Sgr; modulator. This assertion can be justified by considering that the phase detector detects phase which is inherently the integral of the divider output frequency. The two charge pumps (CP) then provide the second integration stage for a second order &Dgr;&Sgr; modulator.
The amount of quantisation noise in the output bit stream for second order noise shaping depends on the reference frequency, f
S
, and the step size of the divider, &dgr;. In general, the divider can divide by n or n+&dgr; where &dgr; might be less than 1. The spectral density of the quantisation error is given approximately by
δ
12
f
s
(
1
-
z
-
1
)
2
&RightBracketingBar;
=
exp
)
j2
Π
fT
s
)
and the full scale input range for the FM deviation is &dgr;f
s
. This is a high pass function which places zeros in the noise at dc. Other noise shaping functions are possible and discussed in the &Dgr;&Sgr; modulator literature.
In general the quantizer need not be restricted to a single bit quantizer. In this case, the output is a multibit digital word, however we still refer to it as a bit stream. The full scale deviation is then p&dgr;f
s
where p is one greater than the number of digital levels in the bit stream. However, the demodulator of
FIG. 1
can also be seen as a PLL. From this PLL point of view, the dual modulus divider (n
+&dgr;) is like a VCO. Applying more 1's to the divider control input (c) causes the divider to divide by the larger modulus more often and, as a result, to have a lower output frequency. The phase of this divider output is sampled relative to the reference frequency in the phase detector (PD). This sampling occurs at the divider output frequency and is integrated in the first charge pump (CP) loop filter. A second charge pump feeding back from the quantiser provides the stabilizing zero necessary for stability in a second order PLL. The presence of the quantiser in this PLL, however, complicates the PLL analogy and as a result the circuit is not often presented from this point of view.
Regardless of whether or not we find it more useful to regard the demodulator as a PLL, the resulting bit stream can then be processed either with digital filtering or analog filtering. If the bit stream is analog filtered with two or more poles in the filter, the high frequency noise can be rolled off to result in a white noise at some low level. It can then be passed directly to the speaker driver.
The primary limitation with this type of demodulator is that the input signal must be sufficiently band limited to remove interfering signals. As well, the signal must be hard limited before entering the demodulator. A practical reason for these requirements is that the input frequency is used to clock the digital logic making up the divider. Under these conditions, the signal must be filtered to the point where the zero crossings of the input signal are substantially unchanged by an interfering signal. In other words, the selectivity must come before the &Dgr;&Sgr; demodulator. This offers no hope of reducing the cost of the IF filter although it does offer a means of demodulation in a single IC.
Another way of looking at the need to filter before entering this demodulator is that both the divider and the edge triggered phase detector can process only information which is contained in the zero crossings of the input signal. In the presence of a strong interferer, the zero crossings are dominated by this interferer, and the demodulator phase locks to the interfering signal. With a very large interferer, the small signal simply rides on top of the interferer and causes only a few zero crossings. As a result, the desired signal can be extracted only by looking at the amplitude information as well. With this theoretical consideration in mind, it seems unfortunate that the original &Dgr;&Sgr; FM demodulators as in
FIG. 1
threw away the amplitude information at the extreme front end of the demodulator.
One approach to demodulation and filters which is most helpful is to consider complex valued signals. The approach taken here is to show that simple phasors are used to describe real signals. This concept of phasors is then extended to include the concept of complex envelope for a bandpass signal. Neither of these constitute a complex signal even though they are complex representations of a real signal.
To take a simple example of the use of phasors, assume we want to find the sum of two voltages that are both sinusoidal functions of time.
s
(
t
)=
A
1
cos (&ohgr;
c
t+&phgr;
1
)+
A
2
cos (&ohgr;
c
t+&phgr;
2
)
To avoid the process of summing up sinusoids in the time domain, each of the sinusoids above can be expressed in complex exponential form i.e.
cos
θ
=
ⅇ
j
θ
+
ⅇ
-
j
θ
2
=
Re
{
ⅇ
j
θ
}
From the above, it is clear that the imaginary part of e
j&thgr;
will always cancel with the imaginary part of e
−j&thgr;
and that the real part is in fact cos
&thgr;
. Similarly, the sum of two sinusoids then becomes
A
1
cos
(
ω
c
t
+
ϕ
1
)
+
A
2
cos
(
ω
c
t
+
ϕ
2
)
=
A
1
ⅇ
j
ω
c
t
+
ϕ
I
+
ⅇ
-
j
ω
c
t
+
ϕ
1
2
+
A
2
ⅇ
j
ω
c
t
+
ϕ
2
+
ⅇ
-
j
ω
c
t
+
ϕ
2
2
=
1
2
[
(
A
1
ⅇ
j
ω
c
t
+
ϕ
1
+
A
2
ⅇ
j
ω
c
t
+
ϕ
2
)
+
(
A
1
ⅇ
(
j
ω
c
t
+
ϕ
1
)
+
A
2
ⅇ
-
j
ω
c
t
+
ϕ
2
)
)
]
Here, the third line groups the sum into two positive frequency exponentials and the sum of two negative frequency exponentials. Again since the sum of two real signals must be another real signal, we would expect that the imaginary parts would cancel out. Some inspection of the equations will reveal that this is true. The convenience of phasor notation comes when we decide to ignore the negative frequency components. S
Cassan Maclean
Kaben Research Inc.
Phu Phuong
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