Motion video signal processing for recording or reproducing – Local trick play processing – With randomly accessible medium
Reexamination Certificate
2000-12-07
2004-10-12
Chevalier, Robert (Department: 2616)
Motion video signal processing for recording or reproducing
Local trick play processing
With randomly accessible medium
C386S349000
Reexamination Certificate
active
06804457
ABSTRACT:
TECHNICAL FIELD
The present invention relates to digital video signal recording and reproducing devices and transmission devices, and more particularly to a digital video signal recording and reproducing device which compresses a digital video signal and records it on a recording medium, and which reads the recorded signal and reproduces it, and to a digital video signal transmission device which compresses a digital video signal and transmits it through a transmission medium.
BACKGROUND ART
Recently, in the field of TV broadcasts, a video signal can be recorded or transmitted in digitized form. At present, the standard-definition television broadcasts mainly use a digital video signal with 480 effective lines and the high-definition television (HDTV) broadcasts mainly use a digital video signal with 1080 effective lines.
Conventional digital video signal recording and reproducing devices for recording and reproducing digital video signals include digital VCRs (Digital Video Cassette Recorders, as D3, D5, etc.), which adopt magnetic tapes (video casettes) as the recording medium. Recently, a standard about consumer-use digital VCRs using very small-sized video cassettes has been formulated (DV standard) and some new products based on the standard have been introduced.
While the DV standards were originally targeted at the standard-definition television broadcasts, they were expanded to the HDTV broadcast later. That is to say, the current DV standards define a compression/recording system about the digital video signal used in the standard-definition television broadcasts (hereinafter referred to as SD) and a compression/recording system for the digital video signal used in the HDTV broadcast (hereinafter referred to as HD).
In the case of SD, the image format of the digital video signal (which is referred to as SD format) uses 480 effective lines for both of luminance and color difference, 720 pixels of horizontal effective samples for luminance and 180 pixels for color difference (4:1:1). In the case of HD, the image format of the digital video signal (which is referred to as HD format) uses 1024 effective lines for luminance and 512 lines for color difference, and 1008 pixels of horizontal effective samples for luminance and 336 pixels for color difference (3:1:0).
A conventional digital video signal recording and reproducing device according to the DV standard <HD> is now described.
FIG. 19
is a block diagram showing the entire structure of the conventional digital video signal recording and reproducing device according to the DV standard <HD>.
In
FIG. 19
, the conventional digital video signal recording and reproducing device according to the DV standard (hereinafter referred to as conventional DV-VCR <HD>) has a compression circuit
170
, a recording circuit
171
, a recording medium
172
, a reproducing circuit
173
, and a decoding circuit
174
.
It is assumed here that a digital video signal for HDTV broadcast <studio standard> is inputted to the conventional DV-VCR <HD>. Its image format uses 1080 effective lines for both of luminance and color difference, 1920 pixels of horizontal effective samples for luminance and 960 pixels for color difference (4:2:2). The recording medium
172
is a magnetic tape.
FIG. 20
is a block diagram showing the structure of the compression circuit
170
of FIG.
19
.
In
FIG. 20
, the compression circuit
170
has a filter circuit
180
, a macro block assembling circuit (DV)
181
, a shuffling circuit
182
, a DCT circuit (DV)
183
, a quantization circuit (DV)
184
, a zigzag scan circuit (DV)
185
, a variable-length encoding circuit (DV)
186
, a DCT mode decision circuit
187
, and a code rate control circuit
188
.
The character “(DV)” indicates a circuit which operates according to the DV standard (which applies hereinafter).
The filter circuit
180
converts the image format of the input digital video signal. The macro block assembling circuit (DV)
181
assembles macro blocks from the output signal of the filter circuit
180
. The shuffling circuit
182
shuffles the output signal of the macro block assembling circuit (DV)
181
. The DCT circuit (DV)
183
applies DCT (Discrete Cosine Transform) to the output signal of the shuffling circuit
182
. The quantization circuit (DV)
184
quantizes the output signal of the DCT circuit (DV)
183
. The zigzag scan circuit (DV)
185
zigzag-scans the output signal of the quantization circuit (DV)
184
. The variable-length encoding circuit (DV)
186
variable-length encodes the output signal of the zigzag scan circuit (DV)
185
.
The DCT mode decision circuit
187
decides whether the DCT should be the 8-8DCT or the 2-4-8DCT defined by the DV standard <HD>. The code rate control circuit
188
controls the code rate of the output of the quantization circuit (DV)
184
.
Referring to
FIG. 19
again, the recording circuit
171
records the output signal of the compression circuit
170
on the magnetic tape. In this process, the recording circuit
171
writes one frame in a region of a predetermined size (20 tracks).
The reproducing circuit
173
reproduces the digital video signal recorded on the magnetic tape.
FIG. 21
is a block diagram showing the structure of the decoding circuit
174
of FIG.
19
.
In
FIG. 21
, the decoding circuit
174
has a variable-length decoding circuit (DV)
190
, a zigzag scan circuit (DV)
191
, an inverse quantization circuit (DV)
192
, an inverse DCT circuit (DV)
193
, a de-shuffling circuit
194
, a reverse macro block assembling circuit (DV)
195
, and a filter circuit
196
.
The variable-length decoding circuit (DV)
190
variable-length decodes the output signal of the reproducing circuit
173
. The zigzag scan circuit (DV)
191
zigzag-scans the output signal of the variable-length decoding circuit (DV)
190
. The inverse quantization circuit (DV)
192
applies inverse quantization to the output signal of the zigzag scan circuit (DV)
191
. The inverse DCT circuit (DV)
193
applies inverse DCT to the output signal of the inverse quantization circuit (DV)
192
. The de-shuffling circuit
194
de-shuffles the output signal of the inverse DCT circuit (DV)
193
. The reverse macro block assembling circuit (DV)
195
assembles a digital video signal from the output signal (macro blocks) of the de-shuffling circuit
194
. The filter circuit
196
reversely converts the image format of the output signal of the reverse macro block assembling circuit (DV)
195
.
Operation of this conventional DV-VCR <HD> is now described.
In
FIG. 19
, a digital video signal is inputted to the compression circuit
170
.
In the compression circuit
170
of
FIG. 20
, first, the filter circuit
180
converts the image format of the input digital video signal from the HDTV broadcast <studio standard> to the DV standard <HD> (i.e. HD format). Next, the macro block assembling circuit (DV)
181
assembles macro blocks from the output signal of the filter circuit
180
.
The operation of the macro block assembling circuit (DV)
181
is now described referring to FIG.
22
.
FIG. 22
is a diagram in assistance of explaining the process in which the macro block assembling circuit (DV)
181
of
FIG. 20
assembles macro blocks from the output signal of the filter circuit
180
, i.e. from the digital video signal (HD format).
In
FIG. 22
, the digital video signal (HD format) is composed of a luminance signal (Y) with 1008 pixels*1024 lines and two color difference signals (Pb, Pr) with 336 pixels*512 lines.
The macro block assembling circuit (DV)
181
extracts 3*2=6 blocks as a unit from the luminance signal (i.e. adjacent 6 blocks including horizontal 3 blocks and vertical 2 blocks), where each block consisting of 8 pixels*8 lines. It also extracts one block composed of 8 pixels*8 lines from each of the two color difference signals. 8 blocks extracted as such are handled as one macro block (in the diagram, the macro block “0”).
The macro block assembling circuit (DV)
181
thus assembles 2688 macro blocks from one frame
Fujiwara Yuji
Miyashita Mitsuhiro
Nishino Masakazu
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