Magnetoresistive random access memory device structures

Details Magnetoresistive random access memory device structures Magnetoresistive random access memory device structures

2003-04-16

2004-08-31

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Magnetic field

C257S225000

Reexamination Certificate

active

06784510

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to magnetoelectronic devices, and more particularly relates to methods for fabricating magnetoresistive random access memory device structures that utilize false magnetic tunnel junction memory element devices and structures for magnetoresistive random access memory devices that utilize false magnetic tunnel junction memory element devices.
BACKGROUND OF THE INVENTION
Magnetoelectronics devices, spin electronics devices and spintronics devices are synonymous terms for devices that use the effects predominantly caused by electron spin. Magnetoelectronics effects are used in numerous information devices, and provide nonvolatile, reliable, radiation resistant, and high-density data storage and retrieval. Magnetoresistive random access memory (MRAM) devices are well-known magnetoelectronics information devices.
One class of MRAM devices is composed of a plurality of arrays of memory elements known as magnetic tunnel junction (MTJ) elements and a plurality of programming lines, typically known as the bit lines and the digit lines, each used to create part of the magnetic field for programming the MTJ elements. An MTJ element in an array generally is electrically coupled to a transistor, typically an N-channel field effect transistor (FET), through an interconnect stack. The interconnect stack is formed using standard CMOS processing that utilizes a number of via and metallization layers, the formation of which requires a number of masking and etching steps. The number of via and metallization layers may vary depending upon the specific devices associated with the memory that are fabricated on the same chip. Formation of the MTJ element coupled to the interconnect stack and formation of its connection to the MRAM device array also utilize a number of masking and etching steps. Each masking and etching step adds to the cost and time required to produce an MRAM device. Thus, even elimination of one such step can result in fabrication cost and time savings.
Accordingly, it is desirable to provide improved methods for fabricating MRAM devices. In addition, it is desirable to provide methods for fabricating MRAM devices that utilize a reduced number of processing steps. Moreover, it is desirable to provide MRAM devices that are fabricated from methods that use a reduced number of processing steps. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.


REFERENCES:
patent: 5734605 (1998-03-01), Zhu et al.
patent: 6587371 (2003-07-01), Hidaka
patent: 6657270 (2003-12-01), Kim et al.
patent: 2003/0142540 (2003-07-01), Tanizaki et al.

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