Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2003-08-01
2004-12-28
Zarneke, David A. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06836130
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of semiconductor manufacturing and more particularly to methods and apparatus for providing wafer scale electrical connections that are particularly useful for testing operations.
2. Background Information
Advances in semiconductor manufacturing processes have resulted in the production of integrated circuits having many millions of transistors as well as other active and passive components. In order to provide for the increased Input/Output (I/O) requirements of such large integrated circuits, the number of I/O pads, or terminals, has increased, while the physical size and the spacing between them (i.e., the pitch) has decreased. As is well-known in this field, many integrated circuits are fabricated at the same time on a substrate which is often referred to as a wafer. These wafers are typically, but not always, formed from a material such as crystalline silicon. The integrated circuits are also referred to in the industry as die, or dice (plural).
Before integrated circuits are provided to customers, and typically before the integrated circuits are packaged, a variety of electrical and functional tests are performed. In order to perform such tests electrical connection must be made with the integrated circuits. Traditionally, such electrical connection is made with the aid of a device referred to as a probe card. The probe tips of the probe card physically contact with the I/O pads of the integrated circuit and provide an electrical pathway between the integrated circuit and various pieces of test equipment which are used to drive the integrated circuit and measure its responses.
What is needed are methods and apparatus for providing cost-effective and reliable means for contacting a large number of I/O pads simultaneously while the integrated circuits are still in wafer form.
SUMMARY OF THE INVENTION
Briefly, methods and apparatus are provided in accordance with the present invention in which the I/O pads of one or more integrated circuits, still in wafer form, are electrically connected to one or more pieces of electrical equipment.
In one embodiment of the present invention, a translator plate is interposed between a wafer and a tester. The translator plate includes a substrate having two major opposing surfaces, each surface having electrical terminals disposed thereon, and electrical pathways disposed through the substrate so as to provide for electrically continuity between at least one electrical terminal on a first surface and at least one electrical terminal on the second surface. The translator plate, when interposed between the wafer and the tester, makes electrical contact with one or more I/O pads of a plurality of integrated circuits on the wafer and provides an electrical pathway therethrough.
In a further aspect of the present invention an anisotropic conductor is disposed between the wafer and the space translator.
In a still further aspect of the present invention, a vibratory mechanism, oriented to provide substantially horizontal vibratory motion to the wafer, is coupled to the wafer during the process of disposing the translator plate and anisotropic conductor over the wafer. In this manner, more reliable electrical connection to the I/O pads is obtained.
REFERENCES:
patent: 4628991 (1986-12-01), Hsiao et al.
patent: 6121065 (2000-09-01), Wong et al.
Nguyen Trung Q.
Werner Raymond J.
Zarneke David A.
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