Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-09-21
2004-02-10
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S720000
Reexamination Certificate
active
06689697
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a planarization process for semiconductor integrated circuit and structures, more particularly to an intermetal dielectric planarization process.
BACKGROUND OF THE INVENTION
In the formation of integrated circuit structures, layers are patterned to form active devices, such as transistors, passive devices, such as resistors, and metal lines. This patterning of layers often creates uneven surfaces which can cause problems to subsequent overlying layers and devices.
Conventionally, a layer of insulating material, such as silicon oxide, is applied over such uneven surfaces to permit the formation of overlying patterned layers. However, the insulating layer (e.g., silicon oxide) tends to conform to the underlying topography resulting in the creation of a non-planar or stepped surface. It is very difficult to pattern further layers over such an uneven surface using standard lithography techniques.
It has become a customary practice to apply planarizing layers of doped oxides, photoresist and organic-based glass materials, such as “SOG” (Spin On Glass). The insulated layer and the planarization layer are then anisotropically etched to remove the planarizing layer and raised sections of the underlying insulating layer.
One of the concerns with creating a uniformly planarized layer is that the dielectric layer, when etched so that the top surfaces of the integrated circuit structures are exposed, falls below the top surface of the integrated circuit structures. Providing a second layer of planarizing type materials such as “SOG” that fill in these depressions in the dielectric layer in between the integrated circuit structures, complicates the etch back procedure as the etching must be controlled precisely and two or more different materials must be etched. Hence, it has been difficult to achieve uniform planarization in an integrated circuit layer that employs a material such as silicon dioxide as the dielectric layer.
SUMMARY OF THE INVENTION
There is a need for a method of forming a layer in a semiconductor device that is uniformly planarized, with requiring use of multiple types of dielectric materials and planarization materials.
This and other needs are met by embodiments of the present invention which provide a method of forming a uniformly planarized structure in a semiconductor wafer. The method comprises the steps of forming metal structures on a substrate layer with spaces between the structures, the top surfaces of the metal structures lying within a common plane. A dielectric material is deposited on the layer, the metal structures and in the spaces. The dielectric layer is first etched so that the dielectric material in the spaces is below the common plane. Additional dielectric material is deposited on the layer, metal structures and in the spaces. The dielectric layer is then etched a second time. Additional dielectric material is then deposited and this material is then etched in repeating fashion until the top of the dielectric layer and the top surfaces of the metal structures have a common, substantially uniform planarization.
The multiple depositions and etchings of the dielectric layer provides a smoothing out of the topography generated due to the conformal nature of the deposition of the dielectric material and the spaces between the integrated surface structures. Repeated depositions and etchings cause the depressions in the spaces between the integrated circuit structures to be reduced with each successive deposition and etching. At some point, the conformal deposition will be relatively smooth so that subsequent etching causes the top of the dielectric layer to be coplanar with the top surfaces of the metal structures. All this is achievable with a single dielectric material, thus providing an advantage over devices that use different materials to provide the uniform planarization. Also, the use of a single material instead of multiple materials provides a uniform dielectric constant throughout the integrated circuit, in contrast to multiple materials that have different ratios of one material to the other at different circuit locations, providing different dielectric constants in those different locations.
The earlier stated needs are also met by another embodiment of the present invention which provides a method of forming a layer of a semiconductor device, comprising the steps of conformally depositing a dielectric material in a dielectric layer over and between integrated circuit (IC) structures having coplanar top surfaces. The dielectric layer is etched such that the top surfaces of the IC structures are free of the dielectric material. These two steps are repeated until the top surface of the dielectric layer between the IC surface structures is coplanar with the top surfaces of the IC surface structures.
The present invention provides the advantages of a uniformly planarized layer with integrated circuit structures and the use of a dielectric layer that does not require two different dielectric materials. The coplanar aspect of the dielectric layer and the top surfaces of the IC circuit structures is readily achieved by well known deposition and etching techniques, using common dielectric materials.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
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patent: 5639345 (1997-06-01), Huang et al.
patent: 5698467 (1997-12-01), Sakao et al.
patent: 6110843 (2000-08-01), Chien et al.
patent: 6117760 (2000-09-01), Gardner et al.
Jiang Chun
Liu Yowjuang (Bill)
Advanced Micro Devices , Inc.
Utech Benjamin L.
Vinh Lan
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