Multiplex communications – Communication techniques for information carried in plural... – Assembly or disassembly of messages having address headers
Reexamination Certificate
2001-01-05
2004-08-31
Vincent, David (Department: 2661)
Multiplex communications
Communication techniques for information carried in plural...
Assembly or disassembly of messages having address headers
C370S509000
Reexamination Certificate
active
06785297
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-011012, filed Jan. 19, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a SDH signal generator, and particularly a SDH signal generator for generating and outputting a SDH signal by increasing/decreasing the AU pointer value contained in that SDH signal by an arbitrary sequence pattern, wherein the sequence pattern can be modified easily.
In the prior art, as shown in
FIG. 6
, in the STM (synchronized transfer mode) system, data is transferred using a SDH (synchronized digital hierarchy) signal wherein 1 frame is composed of a SOH (section overhead) portion of 9×9 bytes and a payload portion of 9×261 bytes.
A value A indicating the information leading head position of the payload portion is inserted as AU (administrative unit) pointer value at the fourth byte of SOH portion of this frame.
In such a system wherein frames are transferred continuously, a phenomenon that the information leading head position of the payload portion is shifted gradually from the position specified by the AU pointer of the initial frame due to the frequency difference between signals during the multiplexing of information of the payload portion, occurs.
To prevent this position shifting, in the STM system of the prior art, data is transferred by adjusting the information leading head position always at the position indicated by the AU pointer, by increasing/decreasing the AU pointer value of the SDH signal.
Consequently, it is necessary to test the response of the transfer system to the AU pointer increase/decrease change, when transfer system is constructed or maintained.
This AU pointer increase/decrease is often executed in a burst shaped pattern, such as increasing the AU pattern by one for Na times successively at a certain repetition cycle &Dgr;TA, and then decreasing the AU pattern by one for Nb times successively at a certain repetition cycle &Dgr;Tb.
Thus, in the SDH signal generator of the prior art, wherein the AU pointer generates SDH signal increasing/decreasing with a predetermined pattern, for instance, a pointer sequence generation circuit
10
as shown in
FIG. 8
is used.
This pointer sequence generation circuit
10
is composed of setting means
11
, first clock means
12
and counting means
13
, second clock means
14
and increase/decrease timing output means
15
.
The first clock means
12
outputs an output instruction signal to the counting means and the increase/decrease timing output means
15
, each time a predetermined time set by the setting means previously has elapsed, from the start until the counting means
13
inputs a number of times completion signal.
The counting means
13
counts the output instruction signal from the first clock means
12
, and outputs the number of times completion signal to the first clock means
12
and the second clock means
14
, when the number of times set by the setting means
11
previously is completed.
The second clock means
14
outputs a next pattern start signal to the first clock means
12
, counting means
13
or increase/decrease timing output means
15
, when the time set by the setting means
11
previously has elapsed from the time of reception of the number of times completion signal from the counting means
13
.
The first clock means
12
resumes to output the output instruction signal by this next pattern start signal, and the counting means
13
resumes the counting.
Upon the reception of output instruction signal from the first clock means
12
, the increase/decrease timing output means
15
outputs a signal indicating the pointer increase timing or a signal indicating the pointer decrease timing fixedly, or alternatively each time when the next pattern start signal from the second clock means
14
is received.
However, as the aforementioned pointer sequence generation circuit lacks flexibility of patterns that can be output, it is necessary to install several set of the circuits for several various sequences, resulting in complication and large-sizing, and moreover, it has been difficult to response to a new sequence.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a SDH signal generator that can solve the problems mentioned above, flexible of sequence patterns to generate, and capable of responding easily to new sequences.
In order to achieve the aforementioned object, according to an aspect of the present invention, there is provided a SDH signal generator, comprising:
a SDH signal generation portion for generating and outputting an SDH signal by increasing/decreasing AU point values contained in the SDH signal, using a sequence pattern made of a plurality of arbitrary combinations of basic patterns, a single basic pattern being made of changing the AU pointer values successively for a predetermined repetition number of times with the same increase/decrease type and repetition cycle; and
a memory storing in a different memory area for each basic pattern, taking the increase/decrease type, repetition cycle and repetition number of times as one set of basic pattern information, for basic patterns used in the SDH signal generation portion, and, storing an address designating the memory area storing the basic pattern information of the basic pattern following its own basic pattern for respective basic pattern.
In order to achieve the aforementioned object, according to another aspect of the present invention, there is provided a SDH signal generator, comprising:
a SDH signal generation portion for generating and outputting an SDH signal by increasing/decreasing AU point values contained in the SDH signal, using a sequence pattern made of a plurality of arbitrary combinations of basic patterns, a single basic pattern being made of changing the AU pointer values successively for a predetermined repetition number of times with the same increase/decrease type and repetition cycle;
a memory storing in a different memory area for each basic pattern, taking the increase/decrease type, repetition cycle and repetition number of times as one set of basic pattern information, for basic patterns used in the SDH signal generation portion, and, storing an address designating a memory area storing the basic pattern information of the basic pattern following its own basic pattern for respective basic pattern;
clock means for outputting an output instruction signal for instructing to output the increase/decrease timing output for increasing/decreasing the AU pointer value each time when a predetermined time has elapsed;
increase/decrease timing output means for outputting a predetermined increase/decrease timing, each time when the output instruction signal is output from the clock means;
counting means for outputting a pattern changeover signal when the output instruction signal is output by the predetermined set number of times, from the clock means; and
parameter setting means for reading out a pattern information stored in a predetermined memory area of the memory upon the reception of a predetermined start signal, setting a repetition cycle contained in the read out pattern information in the clock means as the setting time, setting the increase/decrease timing contained in the read out pattern information in the increase/decrease timing output means, setting the repletion number of times contained in the read out pattern information in the counting means, reading out the pattern information stored in the memory area of the memory designated by the address of the next basic pattern contained in the read out pattern information, upon the reception of the pattern changeover signal from the counting means, and setting respectively in the clock means, the increase/decrease timing output means and the counting means.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the
Anritsu Corporation
Frishauf Holtz Goodman & Chick P.C.
Vincent David
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