Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2002-06-26
2004-11-23
Clark, S. V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S781000
Reexamination Certificate
active
06822336
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, particularly relates to the structure of an electrode for mounting a semiconductor chip.
2. Description of the Prior Art
Recently, IC or LSI has been more and more integrated and the capacity has been increased. A package in which a semiconductor chip is mounted has been small-sized, the number of pins has been increased and the density of the semiconductor chip has been enhanced. Further, a multi-chip package (MCP) in which plural semiconductor chips are mounted has been practically used.
Further, as information technology is rapidly popularized, a demand for the systemization of semiconductor devices that form an information processing unit has grown. The expectation of electronic system integration technology for integrating and systemizing plural LSIs and a versatile functional block including an optical device using a compound semiconductor and a high-frequency device has increased.
In element technique to be the most important in the electronic system integration, minute bonding technique is included. For representative joining technique that has been used, wire bonding technique, flip chip (FC) joining technique and tape automated bonding (TAB) technique can be given, and as particularly the flexibility of bump bonding technique used in the flip chip joining technique is high and high-density connection is enabled, the bump bonding technique is very important. The bump bonding technique is also used in chip on chip (COC) technique which is one of high-density MCP technique.
For the current most general bump bonding technique, technique for melting a solder bump and joining using it called controlled collapsible chip connection (C
4
) is well-known. However, recently, from a viewpoint of conserving global environment, freedom from lead (included in solder) is demanded and a bad effect of the residue after cleaning of flux used for removing an oxide film on the surface of the solder having upon the quality also comes into question.
Then, in place of a solder bump, recently, joining using a gold (Au) bump is discussed. Referring to
FIG. 6
, the outline of the technique will be described below.
FIG. 6
are sectional views showing a schematic process of COC technique for joining two semiconductor chips via a gold bump.
As shown in
FIG. 6A
, a pad electrode
102
is formed in a predetermined region on the surface of a first semiconductor substrate
101
and a first gold bump
103
is formed on the pad electrode
102
. As described above, the first semiconductor chip
104
is formed. Wiring
106
is formed on the surface of a second semiconductor substrate
105
by copper or others and a second gold bump
107
is connected to a predetermined region of the wiring
106
. As described above, a second semiconductor chip
108
is formed.
Next, as shown in
FIG. 6B
, the first semiconductor chip
104
and the second semiconductor chip
108
are overlapped and the first gold bump
103
on the first semiconductor chip
104
and the second gold bump
107
on the second semiconductor chip
108
are aligned. The first gold bump
103
and the second gold bump
107
are bonded, heating and pressurizing them. The temperature of heating is required to be 250° C. or more.
In technique for melting and bonding solder bumps widely used in the current mounting technology, flux is essential to remove an oxide film on the surface of solder. To keep reliability, flux is generally required to be cleaned after bonding is completed, however, it has been difficult to completely clean flux as a bump becomes minute and pitch becomes short. In FC joining using a solder bump, the solder bump is melted and the shape greatly changes. Therefore, there is a limit in shortening pitch between bumps and it is difficult to enhance the density of a semiconductor device.
In the case of FC joining using the gold bumps explained referring to the drawings, the solid phase diffusion of gold is utilized in bonding gold. Then, as described above, the relatively high temperature of 250° C. or more and pressure are required. Therefore, in mounting, IC is damaged and the characteristics of the IC are deteriorated. The problems become more remarkable as the density of IC is enhanced.
In case a copper bump estimated to be able to lower heating temperature in the bonding is applied to an electrode in place of the gold bump based upon prior art, it is very difficult to bond electrodes such as a copper bump because of a copper oxide film easily oxidized at room temperature.
BRIEF SUMMARY OF THE INVENTION
Object of the Invention
The object of the invention is to provide electrode structure which can be joined at low temperature and low energy.
Summary of the Invention
A semiconductor device according to the invention is provided with an electrode used for connecting a semiconductor chip and a wiring board or plural semiconductor chips, an additive layer in which an additive made of at least one type of atom different from the atoms of the electrode is doped in the vicinity of the surface of the electrode and an insulator formed on the surface of the electrode.
REFERENCES:
patent: 5550408 (1996-08-01), Kunitomo et al.
patent: 5869904 (1999-02-01), Shoji
patent: 6232563 (2001-05-01), Kim et al.
patent: 6441496 (2002-08-01), Chen et al.
patent: 6664637 (2003-12-01), Jimarez et al.
patent: 6674016 (2004-01-01), Kubo et al.
Clark S. V.
Katten Muchin Zavis & Rosenman
NEC Electronics Corporation
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