Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
1999-02-12
2004-11-30
Christensen, Andrew (Department: 2615)
Television
Camera, system and detail
Solid-state image sensor
C257S242000, C377S063000
Reexamination Certificate
active
06825879
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an all-pixel readout-type solid-state image sensing device and a method of driving the same and, more particularly, to the structure of a vertical transfer electrode for transferring read signal charges to a vertical CCD (Charge Coupled Device) and setting of a driving voltage to be applied to the vertical transfer electrode.
In recent years, video cameras for business or private use, which use solid-state image sensing devices, are becoming popular. These conventional video cameras for business or private use employ the interlaced scheme (interfaced scanning scheme) with which horizontal signal lines are scanned every other line to cope with the TV scheme (NTSC or PAL).
Meantime, image input cameras for personal computers have been extensively developed recently. Cameras of this type employ, as the horizontal scanning scheme, the non-interlaced scheme to obtain high-resolution still images and easily output images to computer displays. The solid-state image sensing device used in a camera of the non-interlaced scheme must simultaneously and independently read signal charges of all pixels. This read scheme is called all-pixel readout or progressive scan (reference: Okuya et al., “A
⅓-inch
330 k Square-Pixel Progressive-Scan IT-CCD Image Sensor”, 1995 ITE Annual Convention, pp. 93-94, 1995).
FIG. 10
shows a conventional all-pixel readout-type interline CCD solid-state image sensing device.
This image sensing device is mainly divided into an image sensing portion
1
, a horizontal CCD
2
, and an output portion (charge detection portion)
3
. In the image sensing portion
1
, a plurality of photodiodes
4
for storing photoelectrically converted signal charges are two-dimensionally arrayed in a matrix. Vertical CCDs
5
for transferring signal charges in the vertical direction are arranged between the photodiode lines. A transfer gate region
10
for reading signal charges from each photodiode
4
to a corresponding vertical CCD
5
is formed between the photodiode
4
and the vertical CCD
5
. In the image sensing portion
1
, a region other than the photodiodes
4
, vertical CCDs
5
, and transfer gate regions
10
is an element isolation region
11
.
The operation of the solid-state image sensing device with the above arrangement will be described. Signal charges photoelectrically converted by the photodiodes
4
within a predetermined period are read to the vertical CCDs
5
through the transfer gate regions
10
. The signal charges read to the vertical CCDs
5
are transferred to the horizontal CCD
2
in units of horizontal lines. The signal charges transferred to the horizontal CCD
2
are transferred to the output portion
3
and detected.
FIG. 11
shows the photodiodes
4
and vertical CCDs
5
of the solid-state image sensing device shown in FIG.
10
.
FIG. 11
shows only 3×2 pixels in the horizontal and vertical directions.
FIG. 12
shows enlarged details of the structure shown in FIG.
11
.
FIG. 13
shows a section taken along a line C—C in FIG.
12
.
Referring to
FIGS. 11
to
13
, the vertical CCDs
5
consisting of polysilicon and having vertical transfer electrodes
6
,
7
,
8
, and
9
are arranged between the photodiode lines. The four vertical transfer electrodes
6
to
9
are commonly formed across the vertical CCDs
5
in units of photodiodes
4
. The vertical transfer electrodes
8
also serve as transfer electrodes for reading signal charges from the photodiodes
4
to the vertical CCDs
5
. Referring to
FIG. 13
, insulating films (not shown) are formed between a semiconductor substrate
12
and the vertical transfer electrodes
6
to
9
and among the vertical transfer electrodes. Four-phase driving pulses &phgr;V
1
, &phgr;V
2
, &phgr;V
3
, and &phgr;V
4
are applied to the vertical transfer electrodes
6
,
7
,
8
, and
9
, respectively.
A method of driving the vertical CCDs
5
of the above-described solid-state image sensing device of all-pixel readout type will be described next.
FIGS. 14A
to
14
D show the waveforms of driving pulses applied to the vertical transfer electrodes
6
to
9
at the time of read and during the vertical transfer period immediately after the read.
FIGS. 15A
to
15
G show potentials representing signal charge storage and transfer states at times t
0
to t
5
in
FIGS. 14A
to
14
D. The higher the driving pulse voltage becomes, the higher the potential becomes. In
FIGS. 15A
to
15
G, the potential becomes high toward the lower side of the drawings. In other words, the potential with respect to electrons rises toward the upper side of the drawings.
At time t
0
, the driving pulse &phgr;V
3
of high level VH is applied to the vertical transfer electrode
8
also serving as a transfer electrode (
FIG. 14C
) to read signal charges
30
from the photodiode
4
to the vertical CCD
5
, as shown in FIG.
15
B. At this time, the driving pulses &phgr;V
1
and &phgr;V
4
are at low level VL (FIGS.
14
A and
14
D), and the driving pulse &phgr;V
2
is at intermediate level VM (VL<VM<VH) (FIG.
14
B).
At time t
1
, the driving pulse &phgr;V
3
applied to the vertical transfer electrode
8
is set at intermediate level VM (FIG.
14
C), so signal charges are stored only at the lower portions of the vertical transfer electrodes
7
and
8
corresponding to the driving pulses &phgr;V
2
and &phgr;V
3
, respectively, as shown in FIG.
15
C.
At time t
2
, the driving pulse &phgr;V
4
applied to the vertical transfer electrode
9
is set at intermediate level VM (FIG.
14
D), so signal charges are stored only at the lower portions of the vertical transfer electrodes
7
,
8
, and
9
corresponding to the driving pulses &phgr;V
2
, &phgr;V
3
, and &phgr;V
4
, respectively, as shown in FIG.
15
D.
At time t
3
, the driving pulse &phgr;V
2
applied to the vertical transfer electrode
7
is set at low level VL (FIG.
14
B), so signal charges are stored only at the lower portions of the vertical transfer electrodes
8
and
9
corresponding to the driving pulses &phgr;V
3
and &phgr;V
4
, respectively, as shown in FIG.
15
E.
At time t
4
, the driving pulse &phgr;V
1
applied to the vertical transfer electrode
6
is set at intermediate level VM (FIG.
14
A), so signal charges are stored only at the lower portions of the vertical transfer electrodes
8
,
9
, and
6
corresponding to the driving pulses &phgr;V
3
, &phgr;V
4
, and &phgr;V
1
, respectively, as shown in FIG.
15
F.
At time t
5
, the driving pulse &phgr;V
3
applied to the vertical transfer electrode
8
is set at low level VL (FIG.
14
C), so signal charges are stored only at the lower portions of the vertical transfer electrodes
9
and
6
corresponding to the driving pulses &phgr;V
4
and &phgr;V
1
, respectively, as shown in FIG.
15
G.
By sequentially applying the driving pulses, the signal charges
30
are transferred to the left of the drawings, as shown in
FIGS. 15A
to
15
G. Such a driving pulse application method is called double clocking. As the characteristic feature of this method, two or more electrodes are always set at intermediate level VM independently of the states during transfer.
The maximum amount of charges to be transferred by the vertical CCD
5
is limited by the state wherein the driving pulses applied to two vertical transfer electrodes adjacent in the vertical transfer direction are at intermediate level VM, and the driving pulses applied to the remaining vertical transfer electrodes are at low level VL, as at time t
1
, t
3
, or t
5
. That is, the maximum transfer charge amount of the vertical CCD
5
is determined by the amount of charges to be stored in two electrodes adjacent in the vertical transfer direction.
The signal charge read from the photodiode
4
to the vertical CCD
5
will be examined below. Signal charges stored in the photodiode
4
are read by applying a driving pulse of high level VH to the vertical transfer electrode
8
also serving as a transfer electrode. The read voltage required for a complete read depends on a read channel width W
Christensen Andrew
Foley & Lardner LLP
NEC Electronics Corporation
Tran Nhan
LandOfFree
Solid-state image sensing device and method of driving the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Solid-state image sensing device and method of driving the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Solid-state image sensing device and method of driving the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3276526