Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-16
2004-12-07
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185200
Reexamination Certificate
active
06829171
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly to a configuration for reading data at high speed in a non-volatile semiconductor memory device. More particularly, the present invention relates to a configuration for reading data in a non-volatile semiconductor memory device having insulating film charge trapping memory cells each accumulating charges in an insulating film.
2. Description of the Background Art
As a memory storing information in a non-volatile manner, there has been available a collective erasure type EEPROM (electrically erasable and programmable read only memory) having memory cells each constituted of a stacked gate field effect transistor. In the collective erasure type EEPROM or a flash memory, charges are accumulated in a floating gate, made of, for example, polysilicon, insulated from the surroundings and information is stored by altering a threshold voltage of a memory cell transistor according to an accumulated quantity of charges therein.
In the structure of such non-volatile memory cell utilizing a stacked gate field effect transistor, a large electrical stress is applied, in data rewriting, to a tunneling insulating film between a floating gate and a semiconductor substrate region, leading to degradation in the tunneling insulating film. If a defect occurs in such a tunneling insulating film, a charge accumulated in a floating gate is likely to leak out for causing destruction of storage data.
“An insulating film charge trapping non-volatile memory cell” accumulating charges in an insulating film is proposed, as a substitute for a cell structure of a stacked gate field effect transistor that uses a floating gate as a charge accumulating medium.
FIG. 12
is a diagram schematically showing a sectional structure of a conventional insulating film charge trapping memory cell. In
FIG. 12
, an insulating film charge trapping memory cell includes: buried diffusion layers
901
a
and
901
b
formed on a surface of a semiconductor substrate region
900
; a multi-layer insulating film
903
formed between buried diffusion layers
901
a
and
901
b
; and an electrically conductive layer
904
formed on multi-layer insulating film
903
. Diffusion layers
901
a
and
901
b
are formed extending in a column direction and used as bit lines. Conductive layer
904
is formed extending in a row direction, and used as a word line to transmit a row select signal and further as a control gate of a memory cell.
Multi-layer insulating film
903
, though placed extending in the direction of a word line, is depicted in
FIG. 12
as being separated for each memory cell in row direction, in order to emphasize a charge accumulating region of one bit memory cell.
Multi-layer insulating film
903
has a multi-layer structure composed of an oxide film, a nitride film and an oxide film, to accumulate charges in a region of the nitride film. Bit line insulating films
902
a
and
902
b
for isolation of adjacent memory cells are formed on diffusion layers
901
a
and
901
b.
As will be detailed later, adjacent bit lines are isolated by bit line insulating films
902
a
and
902
b
without forming an insulating film for channel isolation. Channel isolation is achieved by a PN junction between a formed channel and a substrate region.
In the memory cell structure shown in
FIG. 12
, a mobility of a charge is small in the insulating film accumulating charges, and therefore, a charge accumulating region is extremely localized. Accordingly, as shown by regions at BT
1
and BT
2
in
FIG. 12
, two charge accumulating regions BT
1
and BT
2
can be formed in one memory cell, thereby enabling storage of 2 bit data in one memory cell.
FIG. 13
is a diagram schematically showing a planar layout of the memory cell shown in FIG.
12
. In
FIG. 13
, there are shown three word lines WL
0
to WL
2
and three bit lines BL
0
to BL
2
as representatives. Word lines WL
0
to WL
2
extend in the row direction and are connected to memory cells arranged on respective rows. Bit lines BL
0
to BL
2
extend in the column direction and are connected to memory cells arranged on respective columns. Each of bit lines BL
0
to BL
2
is shared by memory cells adjacent to each other in the row direction.
Multi-layer insulating film
903
is placed in row direction in parallel to and below word line WL (denoting WL
0
to WL
2
generically). In
FIG. 13
, charge accumulating regions
905
formed of multi-layer insulating film
903
are shown being arranged between bit lines in a similar manner to the structure shown in
FIG. 12
, in order to emphasize a charge accumulating region of each memory cell. In
FIG. 13
, regions
905
hatched by oblique lines are used as charge accumulating regions. Therefore, a nitride film may be formed only in charge accumulating regions
905
hatched by oblique lines. In one charge accumulating region
905
, there are formed effective charge accumulating regions (BT
1
and BT
2
) in which charges corresponding to stored data are accumulated. The effective charge accumulating regions are referred to as right and left bit regions in the following description and data stored in these regions are referred to as a right bit and a left bit, respectively.
Bit lines BL
0
to BL
2
each shared by adjacent memory cells. With respect to one memory cell, one bit line is used as a data line for reading data and the other is used as a source line. A common bit line is used as a data line or a source line, depending on a data access target region.
As shown in
FIG. 13
, a bit line is just provided corresponding to each memory cell column, without a necessity of a dedicated source line. Dissimilar to a conventional stacked gate transistor cell structure, in which charges are accumulated in the polysilicon floating gate, no source line is required, thereby achieving a reduced occupation area of a memory cell. When a design minimum size is indicated F, for example, a pitch between bit lines is represented by 2×F and a pitch between word lines is also represented by 2×F. Accordingly, in
FIG. 13
, a memory cell region
910
represented by broken lines occupies an area of 2F×2F.
Since 2 bit data is stored in one memory cell region
910
, an effective occupation area of a memory cell is 2×F
2
. Furthermore, by changing a quantity of electrons injected into the multi-layer insulating film, a threshold voltage can be changed over multiple levels to enable not only storage of multi-valued data but also more decrease in effective area of a memory cell.
Specifically, in a case where a quantity of injected charges in one effective charge accumulating region (the right bit region or the left bit region) is divided into two levels (a programmed state and an erased state), an effective occupation area of a memory cell is 2×F
2
. In a case where a quantity of injected charges in one effective charge accumulating region is divided into four levels, 2 bit data is stored in one effective charge accumulating region. 4 bit data is stored in one memory cell, and an effective occupation area of a memory cell is 1×F
2
. In a case where an injected charge quantity in an effective charge accumulating region is set over eight levels, an effective occupation area of a memory cell is 0.5×F
2
.
Referring to
FIG. 14
, description will now be given of a write (programming) and read operations of data. In
FIG. 14
, binary data is stored in each of right bit region BT
1
and left bit region and BT
2
. Multilayer insulating film
903
, as shown in
FIG. 14
, includes: a lower side oxide film
903
a
formed on the surface of semiconductor substrate region
900
; a nitride film
903
b
formed on lower side oxide film
903
a
; and an upper side oxide film
903
c
formed on nitride film
903
b
. Charges are accumulated in nitride region
903
b.
Electrically conductive layer (referred to as conductive layer or gate electrode layer hereinafter)
904
functions as a control gate of a memory cell
Hoang Huan
McDermott Will & Emery LLP
Renesas Technology Corp.
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