Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-11-05
2004-10-19
Auduong, Gene N. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185220
Reexamination Certificate
active
06807104
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-347799, filed Nov. 29, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device and a method of programming data into the nonvolatile semiconductor memory device.
2. Description of the Related Art
An electrical connection diagram of a typical NAND EEPROM is shown in FIG.
1
. The NAND EEPROM includes NAND cells as memory cells. The NAND cell is configured by serially connecting cell transistors with the sources of the cell transistors respectively connected to the drains of the adjacent cell transistors. In the NAND cell, since the adjacent cell transistors commonly use the source and drain, the number of contacts between the cells and bit lines can be reduced and it is suitable for high integration. Further, since the gates of a large number of cell transistors are simultaneously driven via a word line WL, data can be programmed into or read out from a large number of cell transistors at high speed.
On the other hand, in the NAND EEPROM, all of the non-selected cell transistors in the NAND cell must be turned ON in order to read out data from a selected cell transistor. Therefore, the threshold voltage of each cell transistor is controlled to be set within a preset range. For example, if the threshold voltage is excessively low, the cell transistor cannot be separated from the non-programmed cell. However, if the threshold voltage is excessively high, the cell transistor cannot be turned ON when it is used as a non-selected cell.
As one example of a method for controlling the threshold voltage of the cell transistor, the flow of a programming method with the verify operation is shown in FIG.
2
. After the program operation is performed by applying program gate potential (Vpgm) to the word line WL, the readout operation is performed by applying verify readout gate potential (Vverify) to the word line WL. At this time, sufficiently high readout gate potential (Vread) is applied to the non-selected word lines WL which are not used for data programming to set the non-selected cell transistors in the ON state. In this state, when the selected cell transistor is turned ON, it is determined that the threshold voltage of the cell transistor is excessively low, that is, a programmed amount is insufficient. Then, Vpgm is raised by a preset amount (&Dgr;Vpgm) and a next program operation is performed. The above technique is called a step-up program technique and described in documents 1 to 3, for example. On the other hand, when the selected cell transistor is turned OFF, it can be determined that the threshold voltage of the cell transistor is made sufficiently high and the program operation is terminated. Since the actual program operation is simultaneously performed for a large number of cell transistors via a word line WL, termination of the program operation indicates that the operation mode is changed into a program inhibition state which will be described later.
FIG. 3
shows an example of a time chart at the data programming time of the NAND EEPROM. In
FIG. 3
, the names of respective nodes correspond to those of FIG.
1
. Assume that the bit line BLk in
FIG. 1
is used as a program bit line and the bit lines BLk+1, BLk−1 are used as program suppression bit lines. At the program time, preset gate potential (Vsg) is applied to the gate of a selection transistor SG
1
on the bit line side. Then, sufficiently low potential (VBLpgm) is applied to the bit line BLk used for programming. Vsg is set to such potential with respect to VBLpgm as to sufficiently turn ON the selection transistor SG
1
. Further, sufficiently high potential (VBLinhibit) is applied to the bit lines BLk+1, BLk−1 used to inhibit the program operation. VBLinhibit is set to such potential as to sufficiently turn OFF the selection transistor SG
1
. When VBLpgm is applied to the bit line, the selection transistor SG
1
is turned ON to transmit VBLpgm to the cell transistor to sufficiently lower the channel potential of the cell transistor so that the program operation can be performed. When VBLinhibit is applied to the bit line BL, the selection transistor SG
1
is turned OFF and the channel potential of the cell transistor is not lowered so that the program operation cannot be performed. This state is the program inhibition state.
At the first program time, after VBLpgm is applied to the bit line BLk connected to the cell transistor to be programmed and VBLinhibit is applied to the bit lines BLk+1, BLk−1 connected to the cell transistors which are inhibited from being programmed, Vpgm is applied to the word line WL. Next, after the bit line BL is charged to preset initial charged potential, Vverify is applied to the word line WL to perform the verify readout operation. When the cell transistor is turned ON and the bit line BL is discharged, a programmed data amount is insufficient, and therefore, the program operation is performed in a next program process. When the cell transistor is turned OFF and the bit line BL is not discharged, a programmed data amount is sufficient, and therefore, the potential of the bit line BL is set to VBLinhibit to set up the program inhibition state in a next program process. The potential of the word line WL is increased to Vpgm+&Dgr;Vpgm to perform an additional program operation with respect to the cell transistor which is determined to have an insufficient programmed data amount. Thus, the verify operation for the threshold voltage of the cell transistor is performed after the program operation and the control operation is performed to determine whether the program operation is performed or inhibited in the next program process based on the result of the verify operation. The above operations are repeatedly performed until the program operations for all of the cell transistors are terminated while the potential of the word line WL is gradually increased. As a result, the threshold voltage of the cell transistor is controlled to be set within a desired range. That is, the lowest threshold voltage of the cell transistor is set to Vverify and the threshold voltage distribution range obtained after the end of the program operation is determined by &Dgr;Vpgm. Therefore, if Vverify is set sufficiently high with respect to the cell which is not to be programmed and Vverify+&Dgr;Vpgm is set sufficiently low with respect to Vread, desired threshold voltage distribution can be attained. A variation in the threshold voltage distribution at the program time of the cell transistor is shown in FIG.
4
.
In
FIG. 4
, if a program characteristic variation of the cell transistor is Wvt, the following conditions must be satisfied in order to attain desired threshold voltage distribution.
First program WL potential: the cell which is programmed at the highest speed is not programmed with voltage equal to or higher than Vverify+&Dgr;Vpgm.
Last program WL potential: the cell which is programmed at the lowest speed is programmed with voltage equal to or higher than Vverify.
During the program operation, it is necessary to increase the program WL potential by the unit of &Dgr;Vpgm, and if the number of program operations to perform the program operations for all of the cell transistors is Nloop, then Nloop is expressed as follows.
N
loop≧
Wvt
/&Dgr;V
pgm
As indicated by the above expression, the number Nloop of program operations becomes larger as the program characteristic variation Wvt of the cell transistor becomes larger. The program characteristic variation Wvt becomes larger as the device is further miniaturized. Therefore, there will occur a problem that the program speed is lowered with the development of miniaturization.
Further, the number Nloop of program operations decreases with a reduction of &Dgr;Vpgm. If &Dgr;Vpgm is reduced, the threshold volta
Arai Fumitaka
Shimizu Akira
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