Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2003-06-26
2004-12-28
Wilson, Allan R. (Department: 2815)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S106000, C438S129000
Reexamination Certificate
active
06835597
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a package for mounting a semiconductor chip (hereinafter called a “semiconductor package”), a process for producing the same, and a semiconductor module using the same, more particularly relates to the structure of an external connection terminal for providing electrical connection with a motherboard or other mounting board when mounting a semiconductor package on a board, specifically to the shape of a pad to which an external connection terminal is bonded.
2. Description of the Related Art
FIG. 1
is a schematic sectional view of a semiconductor package of the related art. A semiconductor package
10
, shown here as a multilayer printed circuit board, mounts a semiconductor chip
1
shown by the broken lines through its electrode terminals
2
. The semiconductor package
10
is provided with a core board
11
, conductor layers
12
including interconnection patterns and pads formed on the two surfaces of the core board
11
, a resin
13
filled in through holes of the core board
11
, second resin layers
14
of the printed circuit board, via holes
15
formed in the resin layers
14
, conductor layers
16
including interconnection patterns and pads formed on the resin layers
14
, third resin layers
17
of the printed circuit board, via holes
18
formed in the resin layers
17
, conductor layers
19
including interconnection patterns and pads formed on the resin layers
17
, protective films
20
formed on the resin layers
17
and conductor layers
19
other than portions of the pads P (
19
) of the conductor layers
19
, pins
21
provided as external connection terminals, and solder
22
for bonding the pins
21
to the pads P (
19
) of the conductor layer
19
exposed from the lower protective film
20
.
The shapes of the pads P (
19
) of the conductor layer
19
exposed from the lower protective film
20
are shown schematically (by the hatchings) as seen planarly along the line A-A′ in the semiconductor package
10
. As illustrated, one pad P is formed for each pin
21
.
FIG. 2
is a schematic view of an example of the layout of interconnections in the semiconductor package
10
. The interconnections (signal lines WS, power line WP, and ground line WG) and pads P are formed,from parts of the conductor layers
19
formed by patterning (FIG.
1
). The interconnections (WS, WP, and WG), are connected to corresponding pads P (
FIG. 2
) and further are connected to pins
21
from the pads through solder
22
(FIG.
1
).
That is, in a semiconductor package of the related art, one interconnection was connected to one external connection terminal (pin) through one pad.
In recent years, along with the demand for greater integration of semiconductor chips, greater density of interconnections and more pins have been demanded, from semiconductor packages mounting them. At the same time, the packages are being asked to be made smaller and thinner. Along with this, the space between pads to which the external connection terminals are bonded is becoming smaller (in the example of
FIG. 2
, 800 &mgr;m). The laying of interconnections at the same interconnection layer is therefore becoming more, difficult space-wise.
Various methods are therefore being applied to deal with this. One of these methods is to widen the space between pads to which the external connector terminals are bonded so as to secure enough space for laying the required interconnections.
Another method is to utilize two or more interconnection layers connected to each other through via holes and lay the interconnections over the interconnection layers and through the via holes when laying the interconnections at the same interconnection layer is difficult.
In the above way, in a semiconductor package of the related art, various methods have been applied to enable the required interconnections to be laid. All of these methods, however, still suffer from problems.
In the method of increasing the space between pads for securing space for laying the interconnections, if trying to keep the number of external connection terminals provided (that is, the number of pads provided) the same, the problem arises that the semiconductor package becomes relatively large in size. This runs counter to the current demand for smaller sized packages. Conversely, if trying to increase the space between pads without changing the package size, the number of the external connection terminals provided has to be reduced. This blocks the greater density of interconnections.
As a method for providing the required number of external connection terminals and securing sufficient space between pads without changing the size of the package, it may be considered to reduce the size of the individual external connection terminals (that is, the size of the individual pads).
With this method, however, it is not possible to secure sufficient reliability of connection since the mechanical bonding strength between the resultantly much smaller external connection terminals and the corresponding resultantly much smaller pads is small. Further, since the external connection terminals are small in size, when mounting the package to the motherboard or other mounting board as well, the bonding strength of the external connection terminals of the package and the mounting board is small and sufficient reliability of connection cannot be obtained.
On the other hand, with the method of using two or more interconnection layers connected through via holes and laying the interconnections over the interconnection layers and through the via holes, since the interconnections which should inherently be laid on the outermost interconnection layers including the pads to which the external connection terminals are bonded (in the example of
FIG. 1
, the conductor layers
19
) are laid with other connection layers through the via holes, there is the disadvantage of an inevitable increase in the number of interconnection layers. This leads to an increase in the thickness of the package and runs counter to the current demand for thinner semiconductor packages.
Further, in current semiconductor packages where greater density is being demanded, even if interconnections can be laid at the same interconnection layer, the interconnection patterns are close to each other, so crosstalk may occur between the interconnections, the potential of the power line etc. may fluctuate, or other problems may occur. In particular, in a package mounting a high frequency use semiconductor chip for which a high speed switching operation is demanded, cross-talk noise easily occurs along with the rise in frequency or switching noise occurs due to the high speed on/off operation of the switching element. Due to this, the potential of the power line etc. easily fluctuates.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor package device raising the freedom of layout of interconnections, facilitating greater compactness and thinness, securing sufficient reliability of connection, and contributing to the reduction of cross-talk noise etc., a process for producing the same, and a semiconductor module using that semiconductor package.
To achieve the above object, according to a first aspect of the present invention, there is provided a semiconductor package provided with an interconnection layer including an interconnection pattern and pad formed on an insulating substrate or insulating layer, a protective layer covering the interconnection layer except at the portion of the pad and the insulating substrate or insulating layer, and an external connection terminal bonded with the pad exposed from the protective layer, the pad to which the external connection terminal is bonded being comprised of a plurality of pad segments, sufficient space being opened for passing an interconnection between pad segments, and the pad segments being comprised of at least one pad segment connected to an interconnection and other pad segments not connected to interconnections.
Since the semicond
Shinko Electric Industries Co. Ltd.
Staas & Halsey , LLP
Wilson Allan R.
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