Flash memory device with distributed coupling between array...

Details Flash memory device with distributed coupling between array... Flash memory device with distributed coupling between array...

2002-08-22

2004-04-06

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185050, C365S185270, C365S185180, C365S185330

Reexamination Certificate

active

06717853

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and apparatus for operating a flash memory cell.
BACKGROUND OF THE INVENTION
Flash memory is a variety of electronic memory in which a specialized field effect transistor is used to store a data value. A binary data value is represented by programming the transistor to have one of two threshold voltage values. Like EEPROM, the threshold voltage value of a Flash memory transistor is programmable by storing and releasing charge on a floating gate structure within the transistor. Unlike EEPROM Flash memory includes a mechanism by which a large number of memory cells may be erased simultaneously. Also, the tunnel oxide layer between a floating gate and a channel region of a Flash memory cell transistor is typically thinner and more uniform than the corresponding oxide layer between the floating gate and channel region of an EEPROM memory cell transistor.
The foregoing will be more fully explained with reference to
FIG. 1
which illustrates a structure of an n-channel flash memory transistor
100
including a source
102
of n-doped semiconductor material, a drain
104
of n-doped semiconductor material, a first insulating layer
106
, a floating gate structure
108
, a second insulating layer
110
, and a control gate structure
112
. The first and second insulating layers are formed of, for example, silicon dioxide. The floating gate and control gate structures are formed of, for example, poly-crystalline silicon (poly).
The transistor
100
is formed in a doped region
114
(e.g., a p-well) of a substrate
116
. The p-well includes a channel region
118
under the first insulating layer
106
. The substrate
116
includes a semiconductor material such as single-crystal silicon. The p-well
114
is bounded at a lower boundary by an implanted region of n-type material
120
, and at a perimeter
122
by a trench of diffusion-doped n-type material
124
.
The transistor
100
is programmed into a particular state by varying an amount of charge stored on the floating gate structure
108
. The state of the transistor is then read by applying a voltage between the drain
104
and source
102
of the transistor and sensing a resulting magnitude of current through the transistor.
In one exemplary flash memory transistor, the floating gate
108
is made of conductive (doped semiconductor) material but is not directly connected to an external source of charge. Charge is added to and removed from the floating gate by injection and tunelling across the first insulating layer
106
. Various mechanisms for charge transfer are known in the art. For example, charge may be added to the floating gate
108
by Channel Hot Electron Injection, and removed from the floating gate
108
by Fowler-Nordheim tunnelling.
In Channel Hot Electron Injection, electrons are accellerated to high velocities by high strength electric fields. These “ballistic” electrons are then propelled by the high fields from the source
102
into the insulating material
106
. A certain proportion of the ballistic electrons traverse the insulator
106
without scattering, and are captured in the floating gate
108
material on the other side. These captured electrons act to increase the quantity of charge on the floating gate
108
.
Fowler-Nodheim (F-N) tunneling depends on the fact that, per quantum mechanics, there is a finite probability that a particle will traverse an energy barrier of finite height, despite the fact that the energy of the particle is insufficient to surmount the energy barrier. Once an electron tunnels from the floating gate
108
into the first insulating layer
106
, it can move freely in the valence or conduction band of the insulator
106
and may thus traverse the insulator. As electrons tunnel out of the floating gate
108
, the charge on the floating gate diminishes. The currents resulting from both Hot Electron Injection and F-N tunneling depend on the respective potentials of the flash transistor source
102
, drain
104
, and control gate
112
.
A first quantity of charge is introduced onto the floating gate structure
108
during an erase operation. To cause this transfer of charge to the floating gate
108
, the source
102
and p-well
114
of the transistor
100
are raised to a high potential such as approximately 9V. This erases the transistor
100
and establishes a first state of the transistor (e.g. a logical zero state). Thereafter, if it is desired to program the transistor to represent a logical one state, the quantity of charge present on the floating gate structure
108
is modified. This is done by applying a potential within a particular range of potentials between the control gate structure and the source and drain of the transistor. Consequently, some electrons tunnel out of the floating gate
108
, across the insulator
106
, and a second quantity of charge is left on the floating gate structure
108
.
The quantity of charge on the floating gate affects the operation of the transistor. Depending on the characteristics of the transistor, the charge on the floating gate may supplement or oppose the effect of a sensing voltage applied to the control gate. For example, in an enhancement mode n-mos transistor, the presence of charges (electrons) on the floating gate attracts holes into the channel region of the transistor and increases its conductivity. Thus, a transistor with a highly charged floating gate exhibits a lower turn-on threshold voltage (Vth) than the same transistor with its floating gate relatively discharged.
Alternately, depending on transistor polarity, the charge stored on the floating gate structure shields the channel region below that gate from the fields of charges introduced into the control gate, and inhibits the accumulation of free carriers within the channel region. Therefore, the threshold voltage of the transistor is again modified by the presence of charge on floating gate.
When exemplary transistor
100
is in an erased state (e.g. programmed to represent a logical zero) the threshold voltage of the transistor is relatively low, and the channel
118
becomes conductive when a sensing voltage is applied to the control gate
112
of the transistor. Conversely, when transistor
100
is programmed to a logical one and a sensing voltage is applied to the control gate
112
of the transistor, the channel
118
remains non-conductive. Thus, substantially no current flows through the transistor between the column line and the array ground node in response to an applied source-drain voltage.
As shown in
FIG. 2
a flash memory device
200
includes a plurality of memory transistors
100
arranged in a two-dimensional array
202
. Along a first dimension of the two dimensional array, the transistors
100
form rows as shown by
204
.
Along a second dimension of the two dimensional array, the transistors
100
form columns as shown by
206
. The device includes a plurality of conductive traces (row lines)
208
(otherwise denominated word lines) disposed along the rows respectively. Each row line
208
is coupled to the respective control gates
112
of the transistors
100
of the respective row
204
. Thus the control gate
112
of every transistor of a row quickly assumes an electrical potential (i.e., a sensing voltage) impressed on the respective row line
208
of the row.
The device
200
also includes a plurality of column lines
210
(otherwise denominated bit lines) disposed along respective columns
206
of transistors
100
. Each column line is coupled to the respective drain
104
of the transistors
100
of a respective column.
The source of every transistor is coupled to an electrical node designated array ground
212
through a plurality of array ground lines
214
. As will be discussed further below, the array ground node is switchingly connectable, by means of a switching device
216
, to a source of reference potential (e.g. ground potential)
218
.
As seen in
FIG. 2
, the array
202
of memory cell transistors
100
is disposed in P-well
114
, the perimeter of which is bounded

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