Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2003-04-25
2004-10-05
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S535000
Reexamination Certificate
active
06800923
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a mixed-signal integrated circuit, and more particularly to the interconnections in a mixed-signal integrated circuit.
2. Description of the Related Art
Mixed-signal integrated circuits, which incorporate both analog and digital circuitry, have become highly integrated, sometimes comprising an entire system on a chip (SoC). Their analog circuitry typically includes high-precision low-noise capacitors having a polysilicon-insulator-polysilicon (PIP) or metal-insulator-metal (MIM) structure with unit capacitance values in the general range from half a femtofarad to two femtofarads per square micrometer (0.5 fF/&mgr;m
2
to 2.0 fF/&mgr;m
2
). These capacitors are interconnected to complementary metal-oxide-semiconductor (CMOS), bipolar CMOS (BiCMOS), and other types of circuits. At high levels of integration, multiple interconnection layers become necessary, the interconnections being routed on complex paths including both horizontal interconnecting lines and vertical contacts and vias.
Contacts connect circuit elements to horizontal interconnecting lines. A capacitor, for example, is typically connected to a horizontal interconnecting line by multiple contacts, to enable the capacitor to be charged and discharged rapidly.
Vias interconnect horizontal interconnecting lines in different layers. Normally two interconnecting lines are interconnected through a single via. This is particularly true in a highly integrated system-on-a-chip, in which layout space is at a premium.
The processes used to fabricate multilayer interconnections involve much use of ionized gases or plasmas. For example, the interlayer dielectric films that provide electrical insulation between different layers are often deposited by plasma-enhanced chemical vapor deposition (PE-CVD) or high-density plasma chemical vapor deposition (HDP-CVD). Contact holes and via holes are formed in the interlayer dielectric films by plasma etching processes. Plasma etching is also used to fashion horizontal interconnecting lines from metal films.
Since these plasma processes are carried out after the MIM or PIP capacitors have already been formed, some of the electrical charge of the plasma is transferred to the capacitors. Since the capacitors are almost always electrically floating, the charge cannot easily escape to the substrate or otherwise be removed.
As a result, when a contact hole or via hole leading directly or indirectly to a capacitor is formed by plasma etching, considerable charge may already have accumulated in the capacitor. At the instant when the hole is completely opened, or slightly thereafter, the capacitor abruptly discharges its accumulated charge through the hole into the plasma. When the via hole closest to the capacitor on the interconnection path is formed, the entire discharge is typically routed through a single via hole.
The sudden concentrated flow of discharge current through a single via hole can damage the floor of the via hole. If, for example, the floor of the via hole comprises a titanium nitride film formed on the surface of the underlying metal interconnecting line, this film may be oxidized and denitrified by the discharge, as observed in electron microscope studies by the inventor. If such damage occurs, then when the via hole is later filled with metal to form an interconnecting via, the via fails to make good electrical contact with the underlying metal interconnecting line, creating an abnormally high electrical resistance on the signal path. The analog circuit including the capacitor then acquires incorrect operating characteristics, or fails to operate at all. Investigations by the inventor have shown that this problem occurs when the total capacitance of the capacitor is 1700 fF or greater.
Further information will be given in the detailed description of the invention.
SUMMARY OF THE INVENTION
A general object of the present invention is to form a mixed-signal integrated circuit with correctly operating capacitive circuit elements.
A more specific object of the present invention is to prevent damage to via holes during the fabrication of a mixed-signal integrated circuit.
The invented mixed-signal integrated circuit includes a metal-insulator-metal or polysilicon-insulator-polysilicon capacitor and an interconnecting line coupled to the capacitor through at least two via holes formed in an interlayer dielectric film deposited by, for example, a high-density plasma deposition process.
The coupling may pass through another interconnecting line. For example, the invented mixed-signal integrated circuit may include a metal-insulator-metal or polysilicon-insulator-polysilicon capacitor, a first interconnecting line connected to the capacitor through one or more contact holes, a first interlayer dielectric film formed on the first interconnecting line, and a second interconnecting line connected to the first interconnecting line through at least two via holes formed in the first interlayer dielectric film. There may also be a second interlayer dielectric film formed on the first interlayer dielectric film and the second interconnecting line, and a third interconnecting line connected to the second interconnecting line through at least two via holes formed in the second interlayer dielectric film.
The invention additionally provides a method of fabricating a mixed-signal IC having a metal-insulator-metal or polysilicon-insulator-polysilicon capacitor covered and surrounded by a first interlayer dielectric film, the first interlayer dielectric film having at least one contact hole extending to the capacitor, the method comprising:
forming a first interconnecting line on the first interlayer dielectric film, the first interconnecting line being electrically connected to the capacitor through said at least one contact hole;
depositing a second interlayer dielectric film on the first interlayer dielectric film and the first interconnecting line by a plasma deposition process;
forming at least two first via holes in the second interlayer dielectric film by a plasma etching process, the first via holes extending to the first interconnecting line; and
forming a second interconnecting line on the second interlayer dielectric film, the second interconnecting line being electrically connected to the first interconnecting line through the first via holes.
In this method, the plasma deposition process charges the capacitor, and the plasma etching process abruptly discharges the capacitor, but since the discharge current is divided among at least two via holes, the amount of discharge current flowing through each via hole is insufficient to damage the floor of the via hole.
Preferably, the capacitor has a total capacitance of at least 1700 femtofarads.
Preferably, the first via holes have respective diameters of at most 0.5 micrometer.
Preferably, among all via holes formed in the mixed-signal IC, the first via holes are electrically closest to the capacitor.
The method may further comprise:
depositing a third interlayer dielectric film on the second interlayer dielectric film and the second interconnecting line by a plasma deposition process;
forming at least two second via holes in the third interlayer dielectric film by a plasma etching process, the second via holes extending to the second interconnecting line; and
forming a third interconnecting line on the third interlayer dielectric film, the third interconnecting line being electrically connected to the second interconnecting line through the second via holes.
The mixed-signal IC may be a system-on-a-chip.
The invention furthermore provides a method of laying out interconnections for a system-on-a-chip IC including a metal-insulator-metal or polysilicon-insulator-polysilicon capacitor, the method comprising:
routing a first interconnecting line in a first interconnection layer to a point above said capacitor, the capacitor being separated from the first interconnection layer by a first interlayer dielectric film;
providing at least one contact hole in the f
Ngo Ngan V.
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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