Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-08-17
2004-04-20
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S725000
Reexamination Certificate
active
06723653
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit structures having copper-filled trenches and/or vias formed in porous low-k dielectric material. More particularly, the invention relates to an improvement in the process of forming such structures wherein rough edges in the pore wall, caused by trench/via etching, are smoothed to provide a superior barrier liner below copper filled-in trench/via.
2. Description of the Related Art
The shrinking of integrated circuits has resulted in levels of electrically conductive interconnects being placed closer together vertically, as well as reduction of the horizontal spacing between the electrically conductive interconnects, such as metal lines, on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO
2
) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled. “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a Flowfill chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The process is said to react methyl silane (CH
3
—SiH
3
) with hydrogen peroxide (H
2
O
2
) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400° C. to remove moisture.
An article by S. McClatchie et al. entitled “Low Dielectric Constant Oxide Films Deposited Using CVD Techniques”, published in the 1998 Proceedings of the Fourth International Dielectrics For ULSI Multilevel Interconnection Conference (Dumic) held on Feb. 16-17, 1998 at Santa Clara, Calif., at pages 311-318, also describes the formation of methyl-doped silicon oxide by the low-k Flowfill process of reacting methyl silane with H
2
O
2
to achieve a dielectric constant of ~2.9.
Another approach to the reduction of capacitance in integrated circuit structures is to lower the dielectric constant (k) by introducing porosity into the dielectric layer. Porous dielectric materials, and methods of making same, are described in Rostoker, Pasch and Kapoor U.S. Pat. No. 5,393,712; Kapoor and Pasch U.S. Pat. No. 5,470,801; Kapoor and Pasch U.S. Pat. No. 5,598,172 (a division of U.S. Pat. No. 5,470,801); and Kapoor and Pasch U.S. Pat. No. 5,864,172 (a continuation of U.S. Pat. No. 5,598,172); all assigned to the assignee of this invention and the subject matter of all of which is hereby incorporated by reference. In these patents, a composite layer is formed on an integrated circuit structure comprising a dielectric material and an extractable material. The extractable material is removed from the composite layer, leaving a porous structure of dielectric material.
The above-mentioned shrinking of integrated circuits and the concurrent ever increasing demands for faster speeds, has also resulted in renewed interest in the use of copper as a filler material for vias and contact openings instead of tungsten, as well as for use in metal lines instead of aluminum because of the well known low electrical resistance of copper, compared to either aluminum or tungsten.
But there are negative aspects to the choice of copper for via filling or in the formation of metal lines. The usual patterning of a blanket-deposited metal layer through a mask to form a pattern of metal lines or interconnects cannot easily be carried out using copper, resulting in the need to first deposit a dielectric layer such as silicon oxide, and then form a series of trenches in the dielectric layer corresponding to the desired pattern of metal lines or interconnects. The trench surfaces are then lined with a diffusion barrier layer or liner (to prevent migration of copper into the dielectric material, as well as to promote adhesion of the filler metal to the trench surfaces), and then filled with copper metal by first forming a copper seed layer over the barrier layer, e.g., by a CVD process, and then filling the remainder of the trench with a blanket deposition of copper, e.g., by a copper plating process.
While the combined use of a porous low-k dielectric material and a copper filler in the trenches and vias etched in such materials can result in the desired reduction in capacitance and enhanced speed, other problems have arisen due apparently to the combined use of a porous dielectric material and a copper filler for the trenches and/or vias etched in such porous dielectric material.
Referring to
FIGS. 1 and 1A
, an integrated circuit structure, denoted as
2
, is shown having a composite layer porous dielectric structure generally indicated at
4
formed thereon comprising a non-porous lower barrier layer
10
of one or more dielectric materials, a porous dielectric layer
20
, and an upper non-porous barrier layer
30
of one or more dielectric materials. An opening
40
is shown formed through dielectric layers
10
,
20
and
30
to form a trench or via opening in composite layer structure
4
.
Formation of such an opening
40
through layers
10
,
20
, and
30
often results in the opening of one or more pores, such as illustrated pore
22
, in porous layer
20
, resulting in the formation of pointed edges
24
remaining on the punctured or ruptured pore
22
, as best seen in FIG.
1
A. When a subsequent barrier liner layer
50
, of e.g. tantalum metal, is then formed as a liner over the etched surfaces of the trench/via opening
40
(as required when using copper filler material), the coverage of barrier liner
50
over the damaged pore
22
is inadequate, resulting in either subsequent non-filling of pore
22
with copper filler
60
, creating a void
62
as shown in prior art
FIG. 2
, or a filling of pore
22
with copper filler, as shown in prior art
FIG. 3
, resulting in direct contact at
66
between copper filler
60
and the porous dielectric material of porous dielectric layer
20
, or a combination of
FIGS. 2 and 3
, as shown in prior art FIG.
4
.
The formation of voids resulting from inadequate filling of pore
22
, as shown in
FIG. 2
, can result in a high resistance or disconnection (open) of copper line
60
at this point. The direct contact between copper filler
60
and porous dielectric layer
20
shown in
FIGS. 3 and 4
can result in diffusion of copper atoms into porous dielectric layer
20
, resulting in degradation of the dielectric properties of porous dielectric layer
20
.
It would, therefore, be desirable to provide a structure and process wherein both a porous dielectric material and a copper filler could be used in the same integrated circuit structure without encountering the deleterious effects just discussed above.
SUMMARY OF THE INVENTION
The invention comprises removal of rough edges in punctured or ruptured pores on the walls of an opening, such as a via and/or trench opening, in a layer of porous dielectric material, in an integrated circuit structure, to permit satisfactory lining of all exposed surfaces of the porous dielectric material with a barrier layer which prevents contact between the copper filler and the porous dielectric material, and facilitates filling of the completely lined punctured/ruptured pore with copper filler to eliminate void formation. The rough edges of the punctured/ruptured pores are removed by an isotropic etch of the exposed walls of the opening. This can be accomplished by adding some isotropicity to the etch used to form the trench/via opening. Preferably, however, the isotropic etch is carried out in a separate step to
Chen Kin-Chan
LSI Logic Corporation
Taylor John P.
LandOfFree
Process for reducing defects in copper-filled vias and/or... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for reducing defects in copper-filled vias and/or..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for reducing defects in copper-filled vias and/or... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3274506