Semiconductor memory device and write/readout controlling...

Details Semiconductor memory device and write/readout controlling... Semiconductor memory device and write/readout controlling...

2002-12-23

2004-09-07

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000

Reexamination Certificate

active

06788562

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor memory device and, more particularly, to an electrically programmable non-volatile semiconductor memory device and a write/read controlling method for the semiconductor memory device.
BACKGROUND OF THE INVENTION
A semiconductor memory device, in which bit lines of a memory cell array are formed by impurity electrically conductive areas provided on a substrate surface, lends itself to increasing the memory capacity, because there is no isolation area between neighboring transistors separating the memory cells and hence the memory cell can be reduced in size. However, such semiconductor memory device is not up to high-speed operations, due to bit-line resistance or stray capacitance, because the bit lines are formed by impurity doped electrically conductive areas provided on a silicon substrate. The bit line length is increased due to increased storage capacity to render the high speed operation difficult. Moreover, since the bit line length is increased, the write voltage applied to a memory cell tends to be lowered due to bit line resistance.
In JP Patent Kokai Publication JP-A-6-283689, for example, there is disclosed a mask ROM configuration in which the resistance of a bit line formed by an electrically conductive region is lowered to provide for a high-speed operation.
FIG. 16
shows a plan view of a memory cell of a semiconductor memory device.
FIG. 17
shows its circuit configuration. On a major surface of a p-type silicon substrate
10
, a plural number of n-type electrically conductive regions (N+ diffusion layers)
11
, operating as source or drain of the memory cell transistor, are arranged parallel to one another at a preset interval in-between. The electrically conductive regions
11
are arranged for traversing the memory cell region and are in the form of a letter U with the web of the letter U being connected with an n-type connecting electrically conductive region
12
for a length equal to two columns. On the outer side of each conducting electrically conductive region
12
is arranged an isolated n-type auxiliary electrically conductive region
13
at a preset distance from each connecting electrically conductive region
12
. On the silicon substrate
10
, carrying these electrically conductive region
11
,
12
and
13
, a plural number of gate electrodes
15
of polycrystalline silicon are arrayed parallel to one another, with the interposition of gate insulating films, for intersecting the electrically conductive regions
11
. The gate electrodes operate as word lines, such that a preset voltage is selectively applied to a row specified by row address data. On both sides of these gate electrodes
15
are arrayed selecting gate electrodes
16
, similarly of polycrystalline silicon, so as to be astride the conducting electrically conductive regions
12
and the auxiliary electrically conductive regions
13
. This forms a selecting transistor T
2
having the selecting gate electrode
16
, connecting electrically conductive regions
12
and the auxiliary electrically conductive regions
13
as its gate, source and drain, respectively. Since this selecting transistor T
2
is provided every four columns on one side of the electrically conductive region
11
, the gate width can be set to a broader value, depending on the size of the auxiliary electrically conductive regions
13
, such that the resistance can be set to a sufficiently small value.
Since the neighboring ones of these selecting transistors T
2
are driven with the common gate electrode, a P-type impurity region
19
is formed between the neighboring selecting transistors T
2
to prevent current conduction across the neighboring selecting transistors T
2
. This device-to-isolation is achieved by for example ion implantation.
In the transistor T
1
, forming each memory cell, the gate electrodes, consecutive from row to row, each form a word line WL. The gate electrodes are selectively activated by selection signals derived from row address data. Similarly, in the selection transistor T
2
, the selecting gate electrodes
16
are common on both sides of the gate electrodes
15
such that the selecting gate electrodes
16
each form a selecting control line SL. An aluminum line
18
forms a main bit line BI, and is selectively activated on receipt of a selection signal derived from column address data. That is, when two of the aluminum lines
18
are specified in dependence upon address data, and the source voltage and the grounding voltage are applied to the so specified aluminum lines, while the selection transistor T
2
connecting to the specified aluminum lines
18
is turned on in order to connect its electrically conductive region
11
to the aluminum lines
18
, the two neighboring columns of the electrically conductive regions
11
are selectively activated. With the two aluminum lines, the voltage applied in the selected state is not fixed to one of the source voltage or to the ground voltage, such that the source voltage is switched to the ground voltage or vice versa depending on the combination of the selected bit lines BL.
In selecting the bit lines BL, either a neighboring pair of the bit lines or a pair of a bit line and a bit line next to the next bit line is selected. Thus, one of the transistors T
1
arranged in a matrix configuration is specified in dependence upon address data and potential variations in the electrically conductive region
11
due to on/off of the MOS transistor T
1
are checked by a sense amplifier, not shown, selectively connected to the aluminum line (main bit line).
Meanwhile, the memory cell of the semiconductor memory device, shown in
FIGS. 16 and 17
, is read-only, such that it does not allow for writing. In a configuration which allows for writing, as in an EEPROM (Electrically Erasable and Programmable Read-Only Memory), a high voltage is applied to the source or to the drain of the memory cell transistor. If the transistor is of the high voltage withstand type to diminish the on-resistance and to suppress the lowering of the current at the time of writing, the junction withstand voltage characteristics are lowered in an impurity layer serving for device isolation across the selecting transistors, thus causing breakdown of the selecting transistor.
In JP Patent Kokai Publication No. JP-A-8-32035, for example, there is disclosed a semiconductor device having two layer gate structure type memory cells, in which a diffusion layer forming local data lines (LDL0 and LDL1) of the memory cell are shared by memory cell MCs provided on a identical column and a diffusion layer forming a local source line (LSL0) is shared by memory cell MCs provided on neighboring two columns, and in which there are provided sub data lines (SDL0 and SDL1) and sub source line (SSL0), which are made up of metal wiring layer having a small sheet resistance, and being arranged in parallel corresponding to the diffusion layers composing common drain and source for coupling between the associated diffusion layer by preset number of contacts (CB and CC).
SUMMARY OF THE DISCLOSURE
Accordingly it is an object of the present invention to provide a programmable semiconductor memory device, employing an electrically conductive layer as an impurity layer, in which the resistance value of the electrically conductive layer by the impurity layer may be diminished and in which the selecting transistors may be of the high voltage withstand type.
It is another object of the present invention to provide a semiconductor memory device in which the voltage may be prevented from being lowered at the time of writing in a memory cell and in which the memory cell readout current may be prevented from being decreased, and a method for writing and readout for the semiconductor memory device. It is yet another object of the present invention to provide a semiconductor memory device in which the sum of the resistance values of the electrically conductive layers by an impurity layer connecting to a memory cell may be kept constant without depende

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