Programmable logic device address buffer/multiplexer/driver

Details Programmable logic device address buffer/multiplexer/driver Programmable logic device address buffer/multiplexer/driver

1990-08-31

1993-02-09

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, 34082522, H03K 1756, H03K 19173

Patent

active

051855399

ABSTRACT:
A programmable logic device having four AND gate means defined therein is used to combine first and second inputs as well as multiplexing and latch signals. These signals are ANDed together (first input and multiplexing signals; inverted multiplexing signal and latch signal and second input; inverted multiplexing signal, second input signal and device output signal; and inverted latch signal and device output signal) to provide four output signals which are ORed together to produce the device output signal.

REFERENCES:
patent: 4675808 (1987-06-01), Grinn
patent: 4677592 (1987-06-01), Sakurai
patent: 4761647 (1988-08-01), Hallenbeck
patent: 4800529 (1989-01-01), Ueno
patent: 4906870 (1990-03-01), Gongwer
patent: 5019736 (1991-05-01), Furtek
patent: 5055718 (1991-10-01), Galbraith
patent: 5122685 (1992-06-01), Chan et al.

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