Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Housing or package filled with solid or liquid electrically...
Reexamination Certificate
2001-08-31
2004-05-25
Zarneke, David A. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Housing or package filled with solid or liquid electrically...
C257S678000, C257S684000, C257S704000, C257S729000, C257S686000, C257S787000
Reexamination Certificate
active
06740964
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package for three-dimensional mounting, a fabrication method thereof, and a semiconductor device. More specifically, the present invention relates to a semiconductor package for three-dimensional mounting which is easy to fabricate and has high packaging density, a fabrication method thereof, and a semiconductor device in which the semiconductor package for three-dimensional mounting is mounted onto a mother board.
2. Description of the Related Art
An example of a conventional BGA (i.e., ball grid array) type semiconductor package is illustrated in FIG.
15
.
As illustrated in
FIG. 15
, a conventional BGA type semiconductor package includes a wiring substrate B and a semiconductor chip A placed on one surface of the wiring substrate B.
A first wiring pattern B
2
is formed at the surface of the wiring substrate B on which the semiconductor chip A is placed, while a second wiring pattern B
4
is formed at a surface of the wiring substrate B opposite the aforementioned surface. The first wiring pattern B
2
and the second wiring pattern B
4
are connected to each other via plated through holes B
6
passing through the wiring substrate B.
The semiconductor chip A and the first wiring pattern B
2
are connected to each other by wires D. A sealing resin layer C is formed at the surface of the wiring substrate B on which the semiconductor chip A is placed. The semiconductor chip A, the first wiring pattern B
2
, and the wires D are embedded in the sealing resin layer C.
On the other hand, the surface of the wiring substrate B on which the second wiring pattern B
4
is provided is covered with a resist layer E formed by a photoresist resin. Openings E
2
are provided at predetermined positions of the resist layer E, and the second wiring pattern B
4
is exposed at the openings E
2
. Solder balls F are connected to the second wiring pattern B
4
exposed at the openings E
2
.
When the above-described BGA type semiconductor package is mounted on a pad of a mother board via the solder balls F, a semiconductor circuit on the mother board is electrically connected to the semiconductor chip A via the pad, the solder balls F, the second wiring pattern B
4
, the plated through holes B
6
, the first wiring pattern B
2
, and the wires D.
However, the BGA type semiconductor packages are mounted onto a mother board only in a two-dimensional manner and cannot be stacked. Thus, there are limitations on the packaging density of the semiconductor packages which can be achieved on a mother board.
Use of small BGA type semiconductor packages can be considered as a means for increasing the packaging density of the BGA type semiconductor packages on the mother board. However, if the BGA type semiconductor packages are made compact, the pitch at which the solder balls are disposed is decreased. Therefore, mother boards manufactured by a buildup process or the like need to be used. As a result, a drawback arises in that mother boards are expensive.
SUMMARY OF THE INVENTION
In view of the aforementioned facts, an object of the present invention is to provide a semiconductor package for three-dimensional mounting which can be mounted at a higher packaging density than conventional BGA type semiconductor packages and is easy to fabricate, a fabrication method thereof, and a semiconductor device formed by mounting the semiconductor package for three-dimensional mounting on a mother board.
A first aspect of the present invention is a semiconductor package for three-dimensional mounting comprising: a first substrate (a wiring substrate) having an upper surface on which a first metal pattern (a first wiring pattern) is formed and a lower surface on which a second metal pattern (a second wiring pattern) is formed, said first metal pattern and second metal pattern being electrically connected to each other; a semiconductor chip which is placed on the upper surface of the first substrate and is electrically connected to the first metal pattern; a sealing resin layer which is formed on the upper surface of the first substrate and seals the semiconductor chip and the first metal pattern; a conductive wire (a thickness direction wire) which passes through the resin layer and has one end electrically connected to the first metal pattern and the other end exposed at a top surface of the resin layer; and a first electrode (a lower surface connecting electrode) which is formed on the lower surface of the first substrate and is electrically connected to the second metal pattern.
When the semiconductor package for three-dimensional mounting is mounted on a pad of a mother board, and then a semiconductor package for three-dimensional mounting having a similar structure or a daughter board is stacked on the semiconductor package for three-dimensional mounting, the lower surface connecting electrode functions as a connecting terminal which electrically connects the semiconductor package for three-dimensional mounting to the mother board. The other end of the thickness direction wire functions as a connecting terminal which electrically connects the semiconductor package for three-dimensional mounting to the semiconductor package for three-dimensional mounting or the daughter board stacked above.
Therefore, the semiconductor chip is electrically connected to the mother board via the first and second wiring patterns on the wiring substrate and the lower surface connecting electrode. Further, the semiconductor chip is electrically connected via the first wiring pattern and the thickness direction wire to a semiconductor chip of the semiconductor package for three-dimensional mounting stacked above or to a semiconductor circuit formed on the daughter board.
A second aspect of the present invention is a semiconductor package for three-dimensional mounting according to the first aspect, further comprising a second substrate (a rewiring substrate) placed on the surface of the resin layer, having an upper surface and a lower surface opposite the upper surface, wherein the second substrate includes a third metal pattern (a third wiring pattern) which is electrically connected to the other end of the conductive wire from the lower surface of the second substrate, and a second electrode (an upper surface connecting electrode) which is formed on the upper surface of the second substrate and is electrically connected to the third metal pattern.
In the semiconductor package for three-dimensional mounting according to the second aspect, the third wiring pattern may be different from the first and second wiring patterns. Thus, connecting wiring which is different from the lower surface connecting electrode at the wiring substrate can be formed at the rewiring substrate.
Moreover, the upper surface connecting electrode can be provided above the semiconductor chip. Therefore, as compared with the semiconductor package for three-dimensional mounting in which the other end of the thickness direction wire is used as the upper connecting electrode, more upper surface connecting electrodes can be formed, and the interval between the upper connecting electrodes can be made larger.
A third aspect of the present invention is a semiconductor package for three-dimensional mounting according to the first or second aspect, further comprising: a fourth metal pattern which is formed on the surface of the resin layer and is electrically connected to the other end of the conductive wire; an insulating layer which covers the fourth metal pattern; and an third electrode which is exposed from the insulating layer and is electrically connected to the fourth metal pattern.
In addition to the advantages of the semiconductor package for three-dimensional mounting according to the second aspect, the semiconductor package for three-dimensional mounting of the third aspect has the advantages that it can be made thinner since no rewiring substrate is necessary and that it is highly reliable.
A fourth aspect of the present invention is a method of fabricating a semicond
Oki Electric Industry Co. Ltd.
Rabin & Berdo PC
Zarneke David A.
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