Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2001-10-02
2004-10-26
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S750000, C257S752000, C257S753000, C438S624000, C438S631000
Reexamination Certificate
active
06809334
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, such as DRAM, and to a method of manufacturing the semiconductor integrated circuit device.
2. Background Art
A semiconductor substrate, such as silicon, is used in a semiconductor integrated circuit device. The semiconductor substrate has a top surface and a back surface, which oppose each other. The top surface of the semiconductor substrate serves as a circuit element fabrication surface on which a plurality of circuit elements, such as transistors or capacitors, are to be fabricated. In contrast, the back surface of the semiconductor substrate is die-bonded to a die pad of a lead frame.
In a semiconductor integrated circuit device, a multilayer interconnection is formed on the surface of a semiconductor substrate for interconnecting circuit elements. In relation to the multilayer interconnection, a TEOS/CVD silicon oxide film is often used as an interlayer dielectric film. The TEOS/CVD silicon oxide film is a silicon oxide film which is to be deposited on the surface of a semiconductor substrate by means of a plasma CVD technique employing TEOS (tetraethylorthosilicate).
FIG. 31
shows a related-art semiconductor integrated circuit device having a TEOS/CVD silicon oxide film. In the semiconductor integrated circuit device, a transistor layer
2
and a capacitor layer
3
are formed on a top surface
1
S of the semiconductor substrate
1
. Further, a multilayer interconnection layer
4
is formed on the capacitor layer
3
. During a process of forming the transistor layer
2
and the capacitor layer
3
on the top surface
1
S, a multilayer film
5
is formed on a back surface
1
B of the semiconductor substrate
1
. During a process of forming a TEOS/CVD silicon oxide film on the top surface
1
S as an interlayer dielectric film of the multilayer interconnection layer
4
, same TEOS/CVD silicon oxide film
6
is formed.
During a process of forming a multilayer interconnection on the surface of the semiconductor substrate
1
, the TEOS/CVD silicon oxide film
6
on the back surface
1
B of the semiconductor substrate
1
still remains as an exposed back surface of the semiconductor substrate
1
. The TEOS/CVD silicon oxide film has the property of being apt to contain or absorb moisture and to produce a gas primarily consisting of moisture upon exposure to a temperature rise. During a process of forming the multilayer interconnection layer
4
, the TEOS/CVD silicon oxide film formed on the top surface
1
S of the semiconductor substrate
1
is coated with an aluminum film, silane other than a TEOS gas, and a silicon oxide film which is formed through plasma CVD through use of oxygen, which make degassing difficult. Hence, a degassing problem does not arise. In contrast, the TEOS/CVD silicon oxide film
6
on the back surface
1
B of the semiconductor substrate
1
remains exposed during the process of forming a multilayer interconnection. Degassing arises as a result of a temperature rise induced by a process of evaporating aluminum on the TEOS/CVD silicon dielectric film on the top surface
1
S, by a process of forming an interlayer film between aluminum layers, or by a process of subjecting an aluminum film to plasma etching. Degassing induces a drop in vacuum or abnormal electric discharge during a vacuum process (such as an aluminum deposition process), a process of forming an interlayer film, and a process of plasma etching of aluminum.
The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the semiconductor integrated circuit device, which obviate occurrence of the foregoing problems.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a semiconductor integrated circuit device comprises: a semiconductor substrate having a top surface and a back surface, which oppose each other; a plurality of circuit elements fabricated on the top surface of the semiconductor substrate along with a TEOS/CVD silicon oxide film; another TEOS/CVD silicon oxide film formed on the back surface of the semiconductor substrate; and a dielectric film, other than the TEOS/CVD silicon oxide film, that does not cause much degassing and that covers the TEOS/CVD silicon oxide film provided on the back surface of the semiconductor substrate.
According to another aspect of the present invention, a semiconductor integrated circuit device comprises: a semiconductor substrate having a top surface and a back surface, which oppose each other; and a plurality of circuit elements fabricated on the top surface of the semiconductor substrate along with a TEOS/CVD silicon oxide film, the TEOS/CVD silicon oxide film not being formed on the back surface of the semiconductor substrate.
According to another aspect of the present invention, a semiconductor integrated circuit device comprises: a semiconductor substrate having a top surface and a back surface, which oppose each other; a plurality of circuit elements fabricated on a top surface of the semiconductor substrate along with a TEOS/CVD silicon oxide film; and a TEOS/CVD silicon oxide film which is formed on the back surface of the semiconductor substrate and involves degassing falling within a tolerance employed in a process of forming a semiconductor integrated circuit device on the semiconductor substrate.
Other features and advantages of the invention will be apparent from the following description taken in connection with the accompanying drawings.
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Fenty Jesse A.
Jackson Jerome
McDermott Will & Emery LLP
Renesas Technology Corp.
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