Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-08-08
2004-03-16
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S195000
Reexamination Certificate
active
06707717
ABSTRACT:
FIELD OF THE INVENTION
The present invention is relative to a current sense amplifier and more particularly to the current sense amplifier with dynamic pre-charge and current biasing method.
BACKGROUND OF THE INVENTION
A memory array consists of plurality of rows of word-lines and a plurality of column of bit-lines. The bit-lines have heavily loaded with parasitic capacitor especially in high density memory array. During read operation, either from standby or normal read access, the parasitic capacitor of the bit-line will be brought to the operating voltage levels of the sense amplifier in order to generate an output indicative of the state of the memory cell being read. But it is hard to control the pre-charge circuit to the desired operating point. If the pre-charge circuit is too strong, the bit-line and the sense line voltage will be overshoot. On the other hand, if the pre-charge circuit is too weak, the pre-charge time will be very long and the bit-line voltage will be under the desired target. Both ways will lead to a very long bit-line recovery time before the sense amplifier can sense the correct state of the memory cell being read.
In this approach, it adopts a new method and circuit for the pre-charge operation. This circuit can quickly pre-charge the bit-line and the sense line being accessed to the operating point. The operating point has self convergence capability in the period of the applied external pulse. Hence it can eliminate the long bit-line recovery time due to the wrong bit-line pre-charge level and reduce the read access time. This pre-charge circuit accompanies with the voltage amplifier and the current mirror. It can provide a new method to bias the current through the current mirror to the desired operating current. Hence It can increase the speed of this current sense amplifier.
Please refer to attachment
1
showing the prior art U.S. Pat. No. 4,713,797. It is a current mirror sense amplifier for a nonvolatile memory. In this prior art, the heavy parasitic capacitor of the bit-line is charged up only by the voltage amplifier itself. Hence the read speed will be limited by the bit-line recovery time due to the weak pull up capability of the voltage amplifier.
Please refer to attachment
2
showing the prior art U.S. Pat. No. 5,258,669. It is a current sense amplifier circuit. In this circuit the bit-lines of the memory cells for the read access process are supplied with a current from the voltage amplifier in addition with the current from a pre-charge circuit in a predetermined short period of time in response to start of the read access.
In this prior art, the bit-line being accessed can be pre-charged quickly, but the bit-line voltage level cannot be controlled to the desired voltage level of the sense amplifier because only pull-up NMOS is being used for the pre-charge operation. It is hard to optimize between pre-charge speed without overshoot. It is difficult to control the pre-charge level (to the operating point of the sense amplifier) so the read access speed cannot be optimized.
Please refer to attachment
3
,
4
showing the prior art
3
(U.S. Pat. No. 5,386,158). It is also a current sense amplifier. In this approach, the pre-charge circuit is self-controlled by the voltage amplifier and no need for pulse control. There are two tradeoffs of this prior art:
1. The time taken for the pre-charge circuit to pre-charge near the VL level is slow because the pre-charge circuit is weak. Hence the amplifier is easily bias to sense the VL level rather than the VH level.
2. The time taken for the voltage amplifier circuit to charge the high parasitic capacitor in the bit-line from the level of VL to VH is quite long because the current supplied by the voltage amplifier alone is weak.
3. The pre-charge circuit cannot accurately pre-charge the bit-line level to the VL as expected due to the Vt difference of the transistors in the pre-charge circuit and the voltage amplifier. This effect makes the first tradeoff even worse.
SUMMARY OF THE INVENTION
The objective of the present invention is to overcome the issues that mentioned in the existing conventional current sense amplifiers (Prior arts). This invention can provide a fast pre-charge current path with clamping mechanism (Both pull up and pull down) to avoid the overshoot of the bit-line voltage during pre-charge period.
According to the present invention, a current sense amplifier with dynamic pre-charge comprises: a storage unit having a sense line; a voltage amplifier for generating a first output signal depending on the sense line; a first current mirror for generating a first current depending on the first output signal; a second current mirror for generating a second current depending on a reference storage unit; and a pre-charge circuit for generating a charge up signal on the sense line to pre-charge the sense line to an operation current level depending on the first output signal, the second current and a clock pulse so as to directly detect a data in the storage unit during detecting the sense line.
In accordance with one aspect of the present invention, the storage unit is a memory cell.
In accordance with one aspect of the present invention, the sense line electrically connects to a bit line of the memory cell.
In accordance with one aspect of the present invention, it further comprises a comparison circuit for comparing the first current and the second current and outputting a data of the storage unit depending on the first current and the second current.
In accordance with one aspect of the present invention, the second current is a reference current and the reference storage unit is a reference memory cell.
According to the present invention, a current sense amplifier with dynamic pre-charge comprises: a storage unit having a sense line; a voltage amplifier for generating a first output signal; a first current mirror for generating a first current depending on the first output signal; a pre-charge circuit for generating a charge up signal on the sense line to pre-charge the sense line to an operation current level depending on the first output signal, an internal reference current and a clock pulse so as to directly detect a data in the storage unit during detecting the sense line.
In accordance with one aspect of the present invention, the storage unit is a memory cell.
In accordance with one aspect of the present invention, the sense line electrically connects to a bit line of the memory cell.
In accordance with one aspect of the present invention, it further comprises a comparison circuit for comparing the first current and the second current and outputting a data in the storage unit depending on the first current and the second current.
In accordance with one aspect of the present invention, the internal reference current is generated from a reference storage unit of the pre-charge circuit.
According to the present invention, a method for biasing a current sense amplifier comprises step of using a pre-charge circuit to set the current sense amplifier near an operating point of the current being sensed in addition with fast sense line pre-charge.
In accordance with one aspect of the present invention, the current is a memory cell current.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which:
REFERENCES:
patent: 4713797 (1987-12-01), Morton et al.
patent: 4943948 (1990-07-01), Morton et al.
patent: 5258669 (1993-11-01), Nakashima
patent: 5386158 (1995-01-01), Wang
patent: 6438051 (2002-08-01), Fifield et al.
Bacon & Thomas PLLC
Hoang Huan
Winbond Electronics Corp.
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