Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2002-05-31
2004-04-13
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C711S105000, C711S111000
Reexamination Certificate
active
06721228
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and more particularly, to a dynamic random access memory (hereinafter, referred to as “DRAM”) using a protocol transmission method, such as Rambus DRAM.
2. Description of the Related Art
As is well known, DRAM is a device for transmitting and receiving digital signals through a bus at a signal received from a central processing unit (CPU). Therefore, it is useless if bus transmission operations are not performed in the DRAM. However, DRAM interface has become a focus of efforts to optimize electric signal transmission by the DRAM, such as the data width of DRAM and the driving force of data output buffer. That is, research and development efforts have been focused on rapid and accurate signal transmission to the outside by the CPU. However, “data transmission” is more important than “bit transmission”. Therefore, it is a more efficient method to transmit data unit having a predetermined size (packet) than to transmit a bit unit signal.
As the paradigm is changed from “bit transmission” processing into “data transmission” processing, Rambus DRAM technology has been developed, using a protocol transmission method. The Rambus DRAM technology employs a method of accessing both DQA and DQB positions in order to rapidly perform data write operations on a memory cell array and data read operations from a memory cell array. That is, first, both DQA and DQB positions of a bank, accessed through a row path such as a row decoder, are activated by a row packet and then, data write and read of DQA and DQB positions are performed through a column path, such as a column decoder, by column packets.
It is necessary to access both DQA and DQB in order to write and read data in certain circumstances. However, there are cases in which either DQA or DQB is selected to write and read necessary data thereon. In that case, according to conventional methods, word lines of DQA and DQB are simultaneously accessed by row packet, and column paths of both DQA and DQB are accessed by column packet, thereby increasing power consumption, as is shown in FIG.
1
. Therefore, a method has been proposed so that the data write operation is performed on a core by masking in order to access the data necessary for data write operations. However, the method also has a problem of high power consumption, since both row path and column path of the accessed bank require access of the DQA and DQB.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made to solve the above-mentioned problems and an object of the present invention is to provide a semiconductor memory device using a protocol transmission method capable of reducing power consumption.
Another object of the present invention is to provide a Rambus DRAM capable of accessing either DQA or DQB.
In order to accomplish the above objects, the present invention comprises a plurality of banks having N subregions, which are simultaneously accessed by activation of one row, and a memory control unit capable of accessing predetermined subregions of the N subregions according to a predetermined field value of a packet.
The banks comprise two subregions, a first subregion and a second subregion, respectively, and it is desirable that either the first subregion or the second subregion or both the first and the second subregions are selectively accessed according to the field value.
In particular, the present invention can be applied to a Rambus DRAM, having DQA and DQB as subregions. In the Rambus DRAM, reserved bits, such as ROWA, ROWR, COLC and COLM packets, are employed to indicate selectively accessed subregions.
As described above, the reserved bits of conventional packet are employed to separately and independently indicate when only DQA or DQB is selectively accessed or both DQA and DQB are accessed. Therefore, it is possible to access only one part of a memory bank in a row operation or in a column operation, thereby reducing the power consumption of a memory.
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patent: 04 222986 (1992-08-01), None
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Ladas & Parry
Nguyen Van-Thu
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