Method for producing a semiconductor memory element

Details Method for producing a semiconductor memory element Method for producing a semiconductor memory element

2002-06-03

2004-04-06

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S240000, C438S253000

Reexamination Certificate

active

06716643

ABSTRACT:

The invention relates to a method for fabricating a contact hole for a semiconductor memory component, in particular a DRAM or an FRAM, having a silicon substrate, an intermediate dielectric layer arranged on said substrate, an upper layer made of a ferroelectric material or made of a material having a high dielectric constant being arranged on said intermediate dielectric layer.
Depending on the chip design or the chip layout, it is necessary, in a large scale integrated DRAM or FRAM, when using materials having a high dielectric constant, for example BST (BST stands for Barium Strontium Titanate), and ferroelectric materials, for example SBT (SBT stands for Strontium Bismuth Tantalate), to etch through these materials during the plasma etching of the contact hole to the silicon substrate. In this case, contamination of the monocrystalline silicon substrate which is uncovered at the bottom of the contact hole must be avoided in order to prevent an adverse effect on the selection transistor of DRAM or FRAM.
For this purpose, it is known to carry out two lithography process steps or two lithography levels. In this case, in the first lithography process step, a window is produced in the ferroelectric layer by plasma etching using a resist mask. In the second lithography process step, the actual contact hole is thereupon etched down to the silicon substrate using a new, smaller resist mask. Although this conventional method leads to the aim of avoiding contamination of the bottom of the contact hole, it is nonetheless very complex on account of the use of two lithography process steps or lithography levels.
DE 43 40 419 C2 discloses a method for fabricating a semiconductor device having an insulating layer in which a contact hole is formed. In this known method, a photoresist perforated mask is formed on the insulating layer and anisotropic etching is carried out to form part of the contact hole whilst leaving a residual layer thickness of the insulating layer. Furthermore, the photoresist mask is removed and a TEOS layer is deposited on the resulting structure. The TEOS layer is then etched anisotropically in order to remove the TEOS layer at the bottom of the partial contact hole. Afterward, the contact hole is completed by means of an etching process, the contact hole having a configuration in which the opening diameter increases through the upward direction.
DE 195 28 746 C1 discloses a method for producing a silicon dioxide layer on surface sections of a structure with sidewall sections and a bottom section.
Accordingly, an object of the present invention consists in providing a method of the type mentioned in the introduction which leads to the aim with a simplified, i.e. a single, lithography process.
This object is achieved by the subject matter of claim
1
. Advantageous developments of the invention are specified in the subclaims.
In other words, the method according to the invention is based on the use of an, organic mask layer which is stable at high temperatures, preferably made of polyimide or photoimide and on the partial etching of the dielectric material layer (intermediate oxide) in combination with the etching-through of the overlying layer made of the material having a high dielectric constant or the ferroelectric material. A depression is thereby achieved in the dielectric layer, except for a residual layer thickness which is less than or equal to the residual thickness of the mask layer after the etching step.
According to the invention, the depression is thereupon sealed laterally by conformal deposition of a layer made of O
3
/TEOS-SiO
2
(TEOS stands for tetraethyl orthosilicate). The process temperature required in this case is typically 400° C. and is tolerated by the perforated mask layer which is stable at high temperatures, without degradation effects.
An oxide etching thereupon uncovers the bottom of the depression in a manner similar to that in the case of a spacer etching, said bottom thereupon being lowered down to the bottom of the contact hole by etching.
The organic layer furthermore serves as a perforated mask and is subsequently removed.
This is advantageously followed by selective renewed deposition of O
3
/TEOS-SiO
2
for the purpose of sealing exclusively the lateral wall of the contact hole and the surface of the wafer, with the bottom of the contact hole being spared. This is followed, in a manner known per se, by contact hole aftertreatment for removing silicon substrate material that is possibly damaged, and metallization of the contact hole.
The method according to the invention thus proceeds more simply than the conventional method with regard to the lithography process.


REFERENCES:
patent: 5478768 (1995-12-01), Iwasa
patent: 5723374 (1998-03-01), Huang et al.
patent: 5780338 (1998-07-01), Jeng et al.
patent: 5814527 (1998-09-01), Wolstenholme et al.
patent: 5914851 (1999-06-01), Saenger et al.
patent: 6030900 (2000-02-01), Grassl et al.
patent: 6097052 (2000-08-01), Tanaka et al.
patent: 6124165 (2000-09-01), Lien
patent: 19640211 (1998-04-01), None
patent: 07-240389 (1995-09-01), None
patent: WO 97/06556 (1997-02-01), None
International Search Report (WIPO).

Affiliated with

Also associated with

Rating

Method for producing a semiconductor memory element does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for producing a semiconductor memory element, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing a semiconductor memory element will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3268433