Pulse or digital communications – Receivers
Reexamination Certificate
2000-01-05
2004-04-13
Tran, Khai (Department: 2631)
Pulse or digital communications
Receivers
C375S260000, C370S536000, C370S542000, C329S327000, C329S363000
Reexamination Certificate
active
06721371
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to an integrated circuit used for receiving communication signals and, in particular, relates to multiple externally programmable integrated circuits used for acquiring and parallel demodulation of radio data communication signals.
2. Prior Art
Modern communication systems, such as Code Division Multiple Access and Time Divisional Multiple Access digital radio communication systems, are typically required to maintain low error rates at high data rates through radio paths that are subject to fading, multipath, and other RF impairments. It is also desirable in many applications to provide the radio receiver in a small, possibly portable package, that makes extensive use of integrated circuit technology. In addition it is also desirable to be able to rapidly demodulate any signal constellation the integrated circuit is capable of demodulating. However, the demodulation of a signal constellation is limited by the rate at which an integrated circuit demodulator may be clocked.
OBJECTS AND ADVANTAGES OF THE INVENTION
It is a first object and advantage of this invention to provide an improved demodulator system capable of demodulating a waveform with a baud rate higher than the highest rate of a single demodulator.
It is a further object and advantage of this invention to provide an array of integrated circuit demodulators where each demodulator comprises a reconfigurable FIR filter in combination with a coherent signal processor, a multi-ported coherent memory, a sequential weight processor, and a dual ported weight memory, all of which can be programmed during use for operating in one of a plurality of modes, including a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode. In addition to the array of parallel integrated circuit demodulators it is a further object and advantage of this invention to provide a one sample per symbol timing interface and a phase reference interface.
SUMMARY OF THE INVENTION
A high speed demodulator system in accordance with this invention includes an analog to digital converter (ADC); a high speed demultiplexer connected to an input of the ADC; a bank of parallel programmable demodulators connected to an output of the high speed demultiplexer; a timing interface connected to the bank of parallel programmable demodulators; and a phase reference interface connected to the bank of parallel programmable demodulators and a data processor. A programmable demodulator in accordance with this invention includes a reconfigurable FIR filter that has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a multi-ported coherent memory. The FIR filter programmably provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a an adaptive sequential weight processor having an input coupled to an output port of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode. Polyphase operation is also within the capabilities of the integrated circuit. In the acquisition mode the FIR filter can be used, in combination with a weight ring and a weight mask, as a PN correlator.
A method for acquiring information signals from a stream of analog signals, the method comprising steps of: digitizing the stream of analog signals to provide a stream of digitized signals; demultiplexing the stream of digitized signals to an array of programmable demodulators demodulating the demultiplexed stream of digital signals through the array of programmable ASICs, and collecting and synchronizing the plurality of outputs of the array of programmable demodulators.
A method of high rate demodulation of a series of modulated analog signals, the method comprising steps of: acquiring and digitizing a series of modulated analog signals; providing parallel programmable demodulation of the digitized series of modulated analog signals; providing a plurality of parallel demodulated data; and reorganizing the demodulated data.
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Bagley Zachary C
Barham Steven T
Horne Lyman D
L-3 Communications Corporation
Perman & Green LLP
Tran Khai
Tran Khanh Cong
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