Preparation method of selective growth silicon layer doped with

Details Preparation method of selective growth silicon layer doped with Preparation method of selective growth silicon layer doped with

1989-04-17

1991-04-02

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437152, 437160, H01L 21225

Patent

active

050047027

ABSTRACT:
A semiconductor substrate having a surface region of P type and a surface region of N type is formed, then an insulating membrane is formed on the semiconductor substrate. The first contact hole which is formed in said region of P type and the second contact hole which is connected to said region of N type are formed by the same process as that for said insulating membrane. Non-doped silicon layer is grown in said first and second contact holes by the same selective growth process, in a single reactive furnace. A diffusion source layer containing impurities of P type is formed on said first contact hole and a diffusion source layer containing impurities of N type on said second contact hole. Impurities are diffused from said diffusion layers to said silicon layers, and said diffusion source layer is then removed. A metal wire layer is formed by connecting it to said silicon layer.

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A. Ipri et al., "Selective Epitaxial Growth for the Fabrication of CMOS Integrated Circuits," IEEE Transactions on Election Devices, vol. ED-31, No. 12, Dec. 1984.
H. Shibata et al., "High Performance Half-Micron PMOSETs with 0.1 .mu.m Shallows P.sup.+ N Junction Utilizing Selective Silicon Growth and Rapid Thermal Annealing," Proceeding of the IEDM (1987).

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