Abrading – Precision device or process - or with condition responsive... – Controlling temperature
Reexamination Certificate
2000-02-14
2004-04-27
Nguyen, George (Department: 3723)
Abrading
Precision device or process - or with condition responsive...
Controlling temperature
C451S053000, C451S449000, C451S285000, C451S287000
Reexamination Certificate
active
06726529
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of semiconductor devices, and more specifically, to a process and apparatus for chemical mechanical polishing.
2. Background Information
Integrated circuits manufactured today are made up of literally millions of active devices such as transistors and capacitors formed in a semiconductor substrate. These active devices are formed and interconnected in an elaborate system of layers. A considerable amount of effort in the manufacture of modern complex, high density multilevel interconnections is devoted to the planarization of the individual layers of the interconnect structure. Nonplanar surfaces create poor optical resolution of subsequent photolithographic processing steps. Poor optical resolution prohibits the printing of high density interconnect metal lines. Another problem with nonplanar surface topography is the step coverage of subsequent metallization layers. If a step height is too large there is a serious danger that open circuits will be created. Planar interconnect surface layers are a must in the fabrication of modern high density integrated circuits.
To ensure planar topography, various planarization techniques have been developed. One approach, known as chemical mechanical polishing, employs polishing to remove protruding steps formed along the upper surface of interlayer dielectrics (ILDs). Chemical mechanical polishing is also used to “etch back” conformally deposited metal layers to form planar plugs or vias.
FIG. 1
illustrates a typical chemical mechanical polisher
100
. As shown, a substrate (or wafer)
110
is held by a carrier
120
. Carrier
120
presses wafer
110
against polishing pad
130
that is attached to polishing platen
140
. Polishing pad
130
is covered with an active slurry
150
and polishing platen
140
rotates in one direction while carrier
120
rotates in the opposite direction. The rotational motion, surface of the polishing pad, and slurry act together to polish or planarize the surface of wafer
110
at ambient temperature (i.e. room temperature).
However, as semiconductor devices become smaller and more dense chemical mechanical polishing is causing some problems with newer materials used to fabricate current semiconductor devices. Prior art materials used in conjunction with chemical mechanical polishing have been relatively hard and/or stiff materials such as oxides, polysilicon, etc. As a result, chemical mechanical polishing processes have been optimized for these materials.
New materials, such as materials with low dielectric constants are being used in order to reduce the RC Time Constant in current semiconductor devices. The RC Time Constant is the fundamental limit of a microprocessor caused by the capacitance between the metal lines of the microprocessor. There are two things which determine the RC Time Constant: the resistance of the metal lines themselves and the capacitance of the dielectric materials.
Silicon dioxide, which is widely used as a dielectric material has a dielectric constant (k) of approximately k=4. However, by switching to materials with lower dielectric constants, for example in the range of approximately k=2-3, several advantages may be obtained. The use of low k polymers have been found reduce the RC Time Constant due to a decreased capacitance and therefore increase the speed of the device. The use of low k materials have also been found to improve power dissipation, and reduce crosstalk noise between metal lines.
Unfortunately, low k materials tend to be more polymers which are more plastic like materials. Therefore, when polishing such low k materials in chemical mechanical polishing, because they are plastic, they tend to bend and/or deform causing bad results and bad uniformity during planarization.
FIG. 2
illustrates a low k material after planarization with prior art chemical mechanical polisher and polishing method. As shown, low k material
210
was deposited above metal lines
220
and substrate
200
. Since low k material
210
is somewhat plastic it deformed during the chemical mechanical polishing process. As illustrated, because low k material
210
deformed during polishing the top surface is not uniform and is not evenly planarized.
Thus, what is needed is a chemical mechanical polisher and polishing process that will enable the planarization of low k materials with good results and uniformity.
SUMMARY OF THE INVENTION
The present invention is a method and apparatus for planarizing by lowering the temperature of the material to be polished and polishing that material at the lowered temperature.
Additional features and benefits of the present invention will become apparent from the detailed description, figures, and claims set forth below.
REFERENCES:
patent: 4450652 (1984-05-01), Walsh
patent: 5127196 (1992-07-01), Morimoto et al.
patent: 5232875 (1993-08-01), Tuttle et al.
patent: 5476817 (1995-12-01), Numata
patent: 5605488 (1997-02-01), Ohashi et al.
patent: 5762537 (1998-06-01), Sandhu et al.
patent: 5775980 (1998-07-01), Sasaki et al.
patent: 5821168 (1998-10-01), Jain
patent: 5851846 (1998-12-01), Matsui et al.
patent: 5873769 (1999-02-01), Chiou et al.
patent: 6121144 (2000-09-01), Marcyk et al.
Cadien Ken
Marcyk Gerald
Intel Corporation
Ortiz Kathleen J.
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