Fault tolerant semiconductor system

Details Fault tolerant semiconductor system Fault tolerant semiconductor system

2002-06-06

2004-09-07

Le, N. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

With electric power receptacle for line wire testing

C324S538000, C716S030000, C716S030000

Reexamination Certificate

active

06788070

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-115210, filed Apr. 17, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor system, a connection test method of the semiconductor system, and a manufacturing method of the semiconductor system and more particularly to a fault tolerant semiconductor system and a fault correction technique for compensating for poor connection of a wiring between a plurality of semiconductor chips, a semiconductor chip and a wiring board or a semiconductor chip and a TAB tape in a semiconductor system having a plurality of semiconductor chips contained in one package.
2. Description of the Related Art
In order to realize data processing with broad band width, it is effective to use a semiconductor system (module) having a plurality of semiconductor chips contained in one package. In the above semiconductor system, it is necessary to make a function test of each semiconductor chip and a connection test between the semiconductor chips after electrical connection between the semiconductor chips is made by use of the flip chip technique, for example.
In this type of semiconductor system, the semiconductor chips are divided into a semiconductor chip (which is hereinafter referred to as a parent chip) having an external I/O and a semiconductor chip (which is hereinafter referred to as a child chip) having no external I/O.
FIG. 1
shows one example of a semiconductor system in which a parent chip
100
and a child chip
200
are arranged with respective main surfaces (element forming surfaces)
10
a
,
200
a
thereof set to face each other and electrodes formed on the element forming surfaces
100
a
,
200
a
of the chips are electrically connected to each other via wirings (bumps)
300
.
In the semiconductor system with the above configuration, it is impossible to directly supply a test signal from the exterior to the child chip
200
having no external I/O. Therefore, a circuit used to transmit/receive a test signal between the parent chip
100
and the child chip
200
and a wiring used to transfer the test signal between the chips are provided.
Conventionally, in the above semiconductor system, a product which is determined to contain poor connection (or connection failure) as the result of the test for connection between the chips is dealt with as a defective product (fail). However, if the semiconductor product is further systemized in future and the number of semiconductor chips and the number of wirings between the chips are increased accordingly, the possibility that poor connection between the chips will occur becomes stronger. Therefore, there occurs a possibility that the manufacturing yield of the products is lowered due to poor connection between the chips and it is desired to take effective measures.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a semiconductor system comprising a plurality of semiconductor chips, a first group of wirings which interconnect the plurality of semiconductor chips, a second group of wirings for redundancy which interconnect the plurality of semiconductor chips, a connection rearrange wiring section including a connection test circuit which makes a test for connection between the plurality of semiconductor chips by the first group of wirings and a connection rearrange circuit which makes unusable the wiring of the first group in which poor connection occurs and rearranges the connection between the semiconductor chips by use of the wiring of the second group when the poor connection is detected in the wiring of the first group by the connection test circuit, and a connection test control circuit which controls the rearrangement of connection between the plurality of semiconductor chips by the connection rearrange wiring section, the connection test control circuit includes a test data generating circuit which generates test data and a coincidence determination circuit which makes a connection test by use of test data formed by the test data generating circuit to determine whether poor connection occurs or not.
According to another aspect of the present invention, there is provided a semiconductor system comprising a plurality of semiconductor chips, a first group of wirings which interconnect the plurality of semiconductor chips, a second group of wirings for redundancy which interconnect the plurality of semiconductor chips, and a connection rearrange wiring section including a connection test circuit which makes a test for connection between the plurality of semiconductor chips by the first group of wirings and a connection rearrange circuit which makes unusable the wiring of the first group in which poor connection occurs and rearranges the connection between the semiconductor chips by use of the wiring of the second group when the poor connection is detected in the wiring of the first group by the connection test circuit, the connection test circuit includes a test data storage element which stores test data and a test result storage element which stores a test result, connection tests are made for the first group of wirings by use of the test data stored in the test data storage element and the test results are stored in the test result storage element.
According to still another aspect of the present invention, there is provided a semiconductor system comprising at least one semiconductor chip, a TAB tape which includes a first group of leads electrically connected to the semiconductor chip and a second group of leads for redundancy electrically connected to the semiconductor chip and on which the at least one semiconductor chip is mounted, and a connection rearrange interconnection section including a connection test circuit which makes a test for connection between the at least one semiconductor chip and the TAB tape and a connection rearrange circuit which makes unusable a lead of the first group in which poor connection occurs and rearranges the connection between the semiconductor chip and the TAB tape by use of the second group of wirings when the poor connection is detected in the lead of the first group by the connection test circuit.
According to still another aspect of the present invention, there is provided a connection test method which is used for a semiconductor system in which a plurality of semiconductor chips are interconnected via wirings, the plurality of semiconductor chips including a connection rearrange wiring section configured by a plurality of blocks each including a connection test circuit and connection rearrange circuit and a connection test control circuit including a test data generating circuit which generates test data and a coincidence determination circuit which detects whether or not poor connection occurs or not, and the connection test circuit including a test data storage element which stores test data and a test result storage element which stores the test result and which makes a connection test for the wirings at the time of boot by control of the connection test control circuit, comprising initializing the test result storage elements in the connection test circuits, generating test data by use of the test data generating circuit and writing the test data into the test data storage elements connected via scan paths, transferring and writing test data between and into the test data storage elements of the plurality of semiconductor chips via the wirings between the semiconductor chips, sequentially reading out values of the test data storage elements provided in the blocks of the plurality of semiconductor chips via the scan paths and sequentially writing the results of coincidence determination made by the coincidence determination circuit into the test data storage elements, recording the results of the connection tests stored in the test data storage elements into the test result storage

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