Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-02-26
2004-05-18
Smith, Matthew (Department: 2825)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110
Reexamination Certificate
active
06738289
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to non-volatile semiconductor memory such as electrically erasable programmable read-only memory (EEPROM) and flash EEPROM, and specifically to circuits and techniques for programming their memory states.
BACKGROUND OF THE INVENTION
Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, retaining its stored data even after power is turned off. In spite of the higher cost, flash memory is increasingly being used in mass storage applications. Conventional mass storage, based on rotating magnetic medium such as hard drives and floppy disks, is unsuitable for the mobile and handheld environment. This is because disk drives tend to be bulky, are prone to mechanical failure and have high latency and high power requirements. These undesirable attributes make disk-based storage impractical in most mobile and portable applications. On the other hand, flash memory is ideally suited in the mobile and handheld environment because of its small size, low power consumption, high speed and high reliability features.
EEPROM and electrically programmable read-only memory (EPROM) are nonvolatile memory that can be erased and have new data written or “programmed” into their memory cells.
An EPROM utilizes a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions.
The floating gate can hold a range of charge and therefore an EPROM memory cell can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell.
For EPROM memory, the transistor serving as a memory cell is typically programmed to a programmed state by accelerating electrons from the substrate channel region, through a thin gate dielectric and onto the floating gate. The memory is bulk erasable by removing the charge on the floating gate by ultraviolet radiation.
FIG. 1A
illustrates schematically a non-volatile memory in the form of an EEPROM cell with a floating gate for storing charge. An electrically erasable and programmable read-only memory (EEPROM) has a similar structure to EPROM, but additionally provides a mechanism for adding and removing charge electrically from its floating gate upon application of proper voltages without the need for exposure to UV radiation.
An array of such EEPROM cells is referred to as a “Flash” EEPROM array when an entire array of cells, or significant group of cells of the array, is electrically erased together (i.e., in a flash). Once erased, the group of cells can then be reprogrammed.
FIG. 1B
illustrates schematically a non-volatile memory in the form of a NROM cell with a dielectric layer for storing charge. Instead of storing charge in a floating gate, it has a dielectric layer for storing charge. For example, U.S. Pat. Nos. 5,768,192 and 6,011,725 disclose a nonvolatile memory cell having a trapping dielectric sandwiched between two silicon dioxide layers.
Cell and Array Structure
FIG. 1C
illustrates schematically a flash EEPROM cell having both a select gate and a control or steering gate. Memory devices having such a cell structure are described in U.S. Pat. No. 5,313,421, which patent is incorporated herein by reference. The memory cell
10
has a “split-channel”
12
between source
14
and drain
16
diffusions. A cell is formed effectively with two transistors T
1
and T
2
in series. T
1
serves as a memory transistor having a floating gate
20
and a control gate
30
. The control gate will also be referred to as a steering gate
30
. The floating gate is capable of storing a selectable amount of charge. The amount of current that can flow through the T
1
's portion of the channel depends on the voltage on the steering gate
30
and the amount of charge residing on the intervening floating gate
20
. T
2
serves as a select transistor having a select gate
40
. When T
2
is turned on by a voltage at the select gate
40
, it allows the current in the T
1
's portion of the channel to pass between the source and drain.
FIG. 1D
illustrates schematically another flash EEPROM cell having dual floating gates and independent select and control gates. Memory devices having such a cell structure are described in co-pending U.S. patent application Ser. No. 09/343,493, filed Jun. 30, 1999, which disclosure is incorporated herein by reference. The memory cell
10
′ is similar to that of
FIG. 1C
except it effectively has three transistors in series. Between a pair of memory transistors, T
1
-left and T
1
-right, is a select transistor T
2
. The memory transistors have floating gates
20
′ and
20
″ and steering gates
30
′ and
30
″ respectively. The select transistor T
2
is controlled by a control gate
40
′. At any one time, only one of the pair of memory transistors is accessed for read or program. When the storage unit T
1
—left is being accessed, both the T
2
and T
1
—right are turned on to allow the current in the T
1
—left's portion of the channel to pass between the source and the drain. Similarly, when the storage unit T
1
—right is being accessed, T
2
and T
1
—left are turned on. Erase is effected by having a portion of the select gate polysilicon in close proximity to the floating gate and applying a substantial positive voltage (e.g. 20V) to the select gate so that the electrons stored within the floating gate can tunnel to the select gate polysilicon.
FIG. 2
is a schematic block diagram of an addressable array of memory cells in rows and columns with decoders. A two-dimensional array of memory cells
100
is formed, with each row of memory cells connecting by their sources and drains in a daisy-chain manner. Each memory cell
50
has a source
54
, a drain
56
and a steering gate
60
and a select gate
70
. The cells in a row have their select gates connected to a word line
110
. The cells in a column have their sources and drains respectively connected to bit lines
124
,
126
. The cells in a column also have their steering gates connected by a steering line
130
.
When the cell
50
is addressed for programming or reading, appropriate programming or reading voltages (V
S
, V
D
, V
STG
, V
SLG
) must be supplied respectively to the cell's source
54
and drain
56
, steering gate
60
and select gate
70
. A word line decoder
112
selectively connects a selected word line to a select voltage V
SLG
. A bit line decoder
122
selectively connects the pair of bit lines
124
,
126
in an addressed column respectively to source voltage V
S
and drain voltage V
D
. Similarly, a steering line decoder
132
selectively connects the steering line
130
in the addressed column to a steering or control gate voltage V
STG
.
Thus, a specific cell of the two-dimensional array of flash EEPROM cells is addressed for programming or reading by a se
Gongwer Geoffrey
Guterman Daniel C.
Malsawma Lex H.
Parsons Hsue & de Runtz LLP
SanDisk Corporation
Smith Matthew
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