Semiconductor memory with multiple timing loops

Details Semiconductor memory with multiple timing loops Semiconductor memory with multiple timing loops

2002-10-24

2004-03-23

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06711092

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to semiconductor memories. More particularly, and not by way of any limitation, the present invention is directed to a system and method for providing multiple timing loops in a memory device with respect to access operatiorns therein.
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a “design gap” between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the “deep submicron” problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that analog blocks, non-volatile memory, random access memories (RAMs), and other “non-logic” cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take hundreds of staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property (“IP”) components—pre-implemented, re-usable modules of, circuitry that can be quickly inserted and verified to create a single-chip system. Such reusable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory is a key technology driver for SOC design. It is also well known that performance parameters such as access time, overall memory cycle time, power consumption, et cetera, play a pivotal role in designing a memory. circuit, whether provided in an embedded SOC application or as a stand-alone device. These parameters can be critically dependent on the topology of a memory array. For high-speed memories, accordingly, it is desirable that these parameters such as access time are optimized regardless of the memory array sizes.
To achieve efficiency, access operations in most memories today are provided to be self-timed. That is, memory accesses typically require only a rising edge of an external clock signal, which is used to manufacture an internal memory clock that provides a time base for access operations. A shutdown signal is subsequently generated for effectuating access shutdown. Thus, in essence, a self-timed clock (STC) is imposed on the memory accesses.
Many techniques are available for generating the self-timed access clock in current memories. Regardless of the implementational variations, the basic concept remains the same: selecting a particular array wordline (WL) based on address signals specified for an access operation, monitoring array bitline(s) (BLs) to determine if they have discharged to a particular level, and turning off the WL at an appropriate time.
It should be appreciated that the conventional STC schemes are highly sensitive to the array sizes because the electrical characteristics—therefore, timing delays—are topology-dependent. As a consequence, while a specific STC arrangement may be satisfactory with respect to a memory device of particular size and aspect, it may be entirely inadequate for other memory sizes. This deficiency is especially exacerbated in compilable memories which, by definition, are capable of generating numerous memory instances having different array sizes, aspect ratios, and I/O configurations, thereby necessitating different delay paths to optimize access timing loops.
SUMMARY OF THE INVENTION
Accordingly, the present invention advantageously provides a semiconductor memory with multiple timing loops for optimizing memory access operations depending upon the array size. A clock generator circuit is provided for generating an internal memory clock based on an external clock or responsive to an input signal transition (e.g., address signal transition) supplied to the memory device. The internal memory clock is operable to provide a timing reference with respect to a memory access operation based on a plurality of address signals. A timing loop selector is operable to select a particular timing loop responsive to at least one or more control signals, referred to as Access Margin (AM) signals, which could be provided from an external source or may be provided as a hardwired option in the circuitry (e.g., as a metal layer option). A shutdown circuit generates an access shutdown signal based on the selected timing loop that is provided with a predetermined delay optimized for the memory's size, speed, aspect ratio, and other performance characteristics.


REFERENCES:
patent: 6198690 (2001-03-01), Kato et al.
patent: 6339553 (2002-01-01), Kuge
patent: 6603687 (2003-08-01), Jun et al.

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