Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-09-12
2004-03-30
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290, C365S185330
Reexamination Certificate
active
06714459
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device enabling high-speed erase where a low threshold is used as an erased state, and to a method of detecting an overerased cell in the nonvolatile semiconductor memory device.
Conventionally, ETOX (EPROM Thin Oxide: brand name of an Intel product) is used as the most commonly used flash memory.
FIG. 12
is a schematic cross sectional view showing this ETOX-type flash memory cell. As shown in
FIG. 12
, a floating gate
5
is formed on a source
1
, a drain
2
and a substrate (well)
3
between the source and the drain via a tunnel oxide film
4
. A control gate
7
is formed on the floating gate
5
via an interlayer insulating film
6
.
The operation principle of the ETOX-type flash memory will be explained below. As shown in Table 1, at the time of write, a voltage Vpp (for example, 10 V) is applied to the control gate
7
, a reference voltage Vss (for example, 0 V) is applied to the source 1, and a voltage of 6 V is applied to the drain
2
. Consequently, a large amount of current is allowed to flow in a channel layer, hot electrons are generated in a portion on the drain
2
side where an electric field is high, and electrons are implanted into the floating gate
5
. As a result, a threshold voltage rises, and data is written to the memory cell.
FIG. 13
shows threshold voltage distributions in a written state and an erased state. As shown in
FIG. 13
, the threshold voltage of a written memory cell is 5 V or higher. It is noted that open of the drain
2
in Table 1 means a voltage applied to the drain
2
of a memory cell to which data is not to be written.
TABLE 1
Control gate 7
Drain 2
Source 1
Substrate 3
Write
10
V
6
V/open
0 V
0 V
Erase
−9
V
Open
6 V
0 V
Read
5
V
1
V
0 V
0 V
Furthermore, at the time of erase, a voltage Vnn (for example, −9 V) is applied to the control gate
7
, a voltage Vpe (for example, 6 V) is applied to the source
1
, and the drain
2
is made open to pull electrons from the floating gate
5
to the source
1
side and lower the threshold voltage. As a result, the threshold voltage of an erased memory cell becomes 1.5-3 V as shown in FIG.
13
.
At the time of read, a voltage of 1 V is applied to the drain
2
and a voltage of 5 V is applied to the control gate
7
. Then, when the memory cell is in an erased state, that is, when the threshold voltage is low, a current is allowed to flow into the cell and its state is determined as “1”. On the other hand, when the threshold voltage is high and the memory cell is in a written state, a current is not allowed to flow into the cell and its state is determined as “0”.
According to such an operation principle as the above, write, erase and read operations are performed. At the time of erase in an actual device, processing is performed in units of relatively large blocks of 64 kB for example. Meanwhile, some memory cells in a block where the erase processing is performed have a threshold voltage in a program state (high voltage) and others have a threshold voltage in an erased state (low voltage). That is, memory cells having two kinds of threshold voltages shown in
FIG. 13
are mixed.
In this case, when an erase pulse is further added to memory cells in an erased state, the threshold voltages of the memory cells already in an erased state become in an excessively erased (overerased) state. Also, when there are memory cells whose threshold voltages decrease more rapidly than those of other memory cells due to variation in erase characteristic, the threshold voltages of the memory cells whose threshold voltages decreases more rapidly than others become in an overerased state. This is particularly problematic when the overerased state progresses, resulting in a negative threshold voltage.
In general, 0 V is applied to control gates of unselected memory cells at the time of read, write-verify or erase-verify. However, when a memory cell having a negative threshold voltage exists among the unselected memory cells, a cell current is allowed to flow into this memory cell although the memory cell is not selected. Therefore, when a selected memory cell M
00
and an overerased cell M (1023, 0) are connected to the same bit line BL
0
as shown in
FIG. 14
, a cell current flowing into the unselected overerased cell M (1023, 0) is added to the cell current flowing into the selected memory cell M
00
. Thus, the cell current measured in the bit line BL
0
has a large value. Therefore, the threshold voltage of a program cell is apparently determined as low (an erased state). Thus, when a memory cell having a negative threshold voltage exists, an operation cannot be performed precisely at the time of the read, write-verify or erase-verify, and, as a result, a normal device operation cannot be performed.
In order to prevent such a problem, a complicated erase algorithm is used at the time of erase so that no memory cell having a negative threshold voltage exists.
FIG. 3
shows the fundamental algorithm.
In
FIG. 3
, when an erase operation is started, first, a program before erase is performed for all memory cells in step S
1
. The voltage applied at this time is the same as that of the write operation described above.
In step S
2
, verify of the program before erase is performed. Detail description thereof is not given here, however, as a result of the verify of the program before erase, if there exists even one memory cell whose threshold voltage does not reach a predetermined voltage (5.0 V or higher in
FIG. 13
) because the program state is insufficient, the program is performed for the memory cell again, and the program and the verify are repeated until the threshold voltage of the memory cell becomes the predetermined voltage (5.0 V) or higher. Then, when the threshold voltage of the memory cell becomes the predetermined voltage (5.0 V) or higher, the program proceeds to the address of the next memory cell. Thus, when threshold voltages of all memory cells become the predetermined voltage or higher, the verify of the program before erase is terminated.
In step S
3
, an erase pulse is applied. This erase pulse application processing is performed in a unit of blocks. That is, data is erased in all memory cells in a block at the same time by making the drain
2
open to apply −9 V to the control gate
7
and 6 V to the source 1.
In step S
4
, when the erase pulse application is terminated as described above, erase-verify is performed to determine whether all memory cells in the block have a predetermined threshold voltage or lower (3 V or lower in this case). Detail description is not given here, but, when a memory cell whose threshold voltage is not the predetermined voltage or lower is found, erase-verify is once stopped, and an erase pulse is applied again. This operation is repeated until threshold voltages of all memory cells become the predetermined voltage or lower.
In step S
5
, overerased cell detection and a soft program described in detail later are performed. Then, the erase operation is terminated.
FIG. 15
shows a general algorithm of the overerased cell detection performed in step S
5
in the flow chart of the erase operation shown in FIG.
3
. Hereafter, operations in the overerased cell detection and the software program will be explained in reference to a flow chart shown in FIG.
15
and array configuration of a flash memory shown in FIG.
2
. In
FIG. 2
, the flash memory cell array is configured by memory cells M arranged in a matrix, word lines WL connected to control gates of the memory cells M arranged in the line direction, bit lines BL connected to drains of the memory cells M arranged in the column direction and a common source line SL for connecting sources of all the memory cells M
00
to M (1023, 511) constituting a block.
In
FIG. 15
, an initial value “0” is set in a column address CA (=bit line BL number) in step S
11
. In step S
12
, an initial value “0” is set in a row address RA (=word line WL number). In step S
13
, a threshold voltage Vt of a m
Mai Son
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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