Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-09-18
2004-10-26
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189020
Reexamination Certificate
active
06809965
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a non-volatile memory. More particularly, this invention relates to a control circuitry to a non-volatile memory. Still more particularly, this invention relates to control circuitry that applies varying voltages to terminals of a memory cell.
2. The Prior Art
Non-volatile memories are common in most processing systems. A non-volatile memory is a memory made of individual memory cells that are commonly transistors. The memory cells in the memory are arranged in rows and columns.
Operations such as read, write and erase, are performed on the memory cells are performed by applying specified voltages to terminals of the individual cells. Typically, a row latch is used to apply a voltage to one terminal of individual memory cells in a specified row to perform an operation and a column latch is used to apply a second voltage to a second terminal of the individual memory cells in a specified column to perform the operation. The row latch commonly applies voltages to the gate of the transistor in the individual memory cells. The column latch commonly applies voltages to the drain of the transistor of the individual memory cells in a column.
Typically, the voltages applied to the terminals by the column latch and row latch are generated by circuitry in the memory system. As non-volatile memories get smaller, the requirements for the voltages applied to the terminal of individual memory cells become more complex. For example, some operations may require successive or simultaneous application of differing potential to the terminals of identical memory elements. Therefore, there is a need in the art for circuitry that provides these different voltages in a timely and consistent manner.
BRIEF DESCRIPTION OF THE INVENTION
The above and other problems are solved and an advance in the art is made by the control circuitry of non-volatile memory in accordance with this invention. In accordance with this invention, the control circuitry of a memory may apply simultaneously differing voltages to multiple individual memory cells. Control circuitry, designed in accordance with this invention, is made economical through the minimal use of transistors in the circuit to control the voltages.
In accordance with this invention, the control circuitry has a first or row circuitry that is configured to provide one of a first group of voltages to an individual memory based upon the row of the memory cell and the operation to be performed. The control circuitry also has second or column circuitry that applies a second voltage from a second group of voltages to the memory cell based upon the column of the cell and the operation to be performed.
In accordance with this invention, the first circuitry of the control circuitry may in row latch circuitry. The row latch circuitry has a first input that receives a high voltage and a second input that receives a low voltage. The row latch circuitry then selects either the high voltage or the low voltage to apply to the memory cell. An output of the row latch circuitry then applies the selected voltage to the memory cell.
A high voltage multiplexer may have an output connected to the row latch circuitry. The high voltage multiplexer has inputs that each receives one of a group of high voltages and an output that applies one of the received high voltages to the row latch circuitry.
A low voltage multiplexer may also have an output connected to the row latch circuit to provide the low voltage. The low voltage multiplexer inputs each receives one of a group of low voltages. A low voltage from the group is then selected and an output applies the selected low voltage to the row latch circuitry.
Selection circuitry may also be connected to the row latch circuitry. The selection circuitry applies a control signal to the row latch circuitry. The row latch circuitry determines which of the voltages to apply to the memory cell based upon the control signal. The selection circuitry may include a signal line, an inverter connected to the signal line, and a word line multiplexer that has inputs connected to the signal line and the inverter. The word line multiplexer selectively applies either the signal or an inverted signal to the row latch circuitry.
In accordance with this invention, the second circuit may include column latch circuitry. The column latch circuitry may include a first input that receives a high voltage and a second input that receives a low voltage. The circuitry then selects one of the voltages. An output of the column latch circuitry applies the selected voltage to the memory element.
The second circuitry may also include word latch circuitry. The word latch circuitry has inputs that each receives one of a group of high voltages. The word latch circuitry selects one of the received high voltages and an output of the word latch circuitry applies the selected high voltage to the column latch circuitry.
A first input of the word latch circuitry may be connected to an output of a first multiplexer. The first multiplexer receives at least two of high voltage signals outputs one of the received high voltages. A second input of the word latch circuitry may be connected to an output of a second multiplexer. The second multiplexer receives two more high voltage signals and outputs one of the high voltages to an input of the word latch circuitry.
The low voltage for the column latch circuitry may be received from a low voltage multiplexer. The low voltage multiplexer receives a group of low voltage signals and outputs one of the low voltage signals to said column latch circuitry.
REFERENCES:
patent: 5187683 (1993-02-01), Gill et al.
patent: 5341329 (1994-08-01), Takebuchi
patent: 5557572 (1996-09-01), Sawada et al.
patent: 5896316 (1999-04-01), Toyoda
patent: 6314025 (2001-11-01), Wong
Nguyen Van-Thu
Sierra Patent Group Ltd.
Virtual Silicon Technology, Inc.
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