Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2002-10-25

2004-03-09

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S189050

Reexamination Certificate

active

06704242

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having input circuits for receiving input signals.
2. Description of the Related Art
Recently, semiconductor integrated circuits are ever decreasing in power supply voltage (operation voltage) for the sake of finer transistor structures, reduced power consumption, and so on. The threshold voltages of the transistors hardly depend on the power supply voltage. With the decreasing power supply voltage, the threshold voltages of the transistors thus increase in relation to the power supply voltage. As a result, circuits made of transistors tend to decrease in operation margin.
FIG. 1
shows an example of an input circuit for receiving an input signal supplied from exterior.
The input circuit has a latching part
1
, a precharging part
2
, a feedback part
3
, an input part
4
, a power supply connection part
5
, and a buffer part
6
. The latching part
1
is composed of two CMOS inverters
1
a
and
1
b
having inputs and outputs connected to each other. The precharging part
2
is composed of two pMOS transistors
2
a
and
2
b
which are connected at their drains to the input nodes ND
1
and ND
2
of the CMOS inverters
1
a
and
1
b
, respectively. The pMOS transistors
2
a
and
2
b
are connected to a power supply line VDD at their sources, and receive a clock signal CLK at their gates.
The feedback part
3
is composed of two nMOS transistors
3
a
and
3
b
which are connected at their drains to the sources of the nMOS transistors of the CMOS inverters
1
a
and
1
b
. The gates of the nMOS transistors
3
a
and
3
b
receive the inverted levels of the nodes ND
2
and ND
1
(/ND
2
and /ND
1
) which are supplied through the buffer part
6
, respectively. The input part
4
is composed of nMOS transistors
4
a
and
4
b
which are connected at their drains to the sources of the nMOS transistors of the CMOS inverters
1
a
and
1
b
. The gates of the nMOS transistors
4
a
and
4
b
receive an input signal IN and a reference voltage VREF, respectively. The reference voltage VREF is set at a central voltage between the high-level voltage and low-level voltage of the input signal IN.
The power supply connection part
5
consists of an nMOS transistor
5
a
which is connected at its drain to the sources of the nMOS transistors
3
a
,
3
b
,
4
a
, and
4
b
. The nMOS transistor
5
a
is connected to a ground line VSS at its source, and receives the clock signal CLK at its gate. The buffer part
6
has inverters
6
a
and
6
b
for inverting the logic levels of the nodes ND
1
and ND
2
, respectively, and an output circuit
6
c
. The output circuit
6
c
has a pMOS transistor and an nMOS transistor arranged in series between the power supply line VDD and the ground line VSS. The gate of the pMOS transistor of the output circuit
6
c
is connected to the node /ND
1
through an inverter. The gate of the nMOS transistor of the output circuit
6
c
is connected to the node /ND
2
.
In the input circuit shown in
FIG. 1
, when the clock signal CLK is at low level, the pMOS transistors
2
a
and
2
b
of the precharging part
2
turn on so that the input nodes ND
1
and ND
2
of the CMOS inverters
1
a
and
1
b
both change to high level. Here, the nMOS transistor
5
a
is off. While the nodes ND
1
and ND
2
are at high level, the outputs of the inverters
6
a
and
6
b
of the buffer part
6
. i.e., the nodes /ND
1
and /ND
2
are low in level, turning off the nMOS transistors
3
a
and
3
b
of the feedback part
3
.
Next, the input signal IN is supplied before the clock signal CLK changes to high level. The clock signal CLK of high level turns off the pMOS transistors
2
a
,
2
b
of the precharging part
2
and turns on the nMOS transistor
5
a
of the power supply connection part
5
. For example, if the input signal is at high level (a voltage higher than the reference voltage VREF), the source-to-drain resistance of the nMOS transistor
4
b
becomes lower than that of the nMOS transistor
4
a
. Consequently, the node ND
1
falls below the node ND
2
in voltage. The source-to-drain resistance of the pMOS transistor
1
a
becomes lower than that of the pMOS transistor
1
b
. As a result, the node ND
2
rises in voltage and the node ND
1
falls in voltage. That is, the high level of the input signal IN is latched into the latching part
1
.
The low level of the node ND
1
and the high level of the node ND
2
change the nodes /ND
1
and /ND
2
to high level and low level, respectively. The output circuit
6
c
of the buffer part
6
receives the low level of the node /ND
2
and the inverted level (low level) of the node /ND
1
, and changes the output signal OUT to high level. That is, the logic level of the input signal IN latched in the latching part
1
is output.
Since the nMOS transistor
3
b
of the feedback part
3
turns on in response to the high level of the node /ND
1
, the latching state of the latching part
1
is fixed regardless of the level of the input signal IN. The latching part
1
latches the input signal IN until the clock signal CLK changes to low level.
FIG. 2
shows another example of the input circuit. This input circuit is the input circuit shown in
FIG. 1
, inverted in polarity. More specifically, the nMOS transistors and pMOS transistors, as well as the power supply line VDD and ground line VSS, are replaced with each other.
The input circuit has a latching part
1
, a precharging part
7
, a feedback part
8
, an input part
9
, a power supply connection part
10
, and a buffer part
11
. The precharging part
7
is composed of two nMOS transistors,
7
a
and
7
b
which are connected at their drains to the input nodes ND
1
and ND
2
of the CMOS inverters
1
a
and
1
b
, respectively. The nMOS transistors
7
a
and
7
b
are connected to a ground line VSS at their sources, and receive a clock signal /CLK at their gates. The clock signal /CLK is the clock signal CLK inverted in phase.
The feedback part
8
is composed of two pMOS transistors
8
a
and
8
b
which are connected at their drains to the sources of the pMOS transistors of the CMOS inverters
1
a
and
1
b
. The gates of the pMOS transistors
8
a
and
8
b
receive the inverted levels of the nodes ND
2
and ND
1
(/ND
2
and /ND
1
) which are supplied through the buffer part
11
, respectively. The input part
9
is composed of pMOS transistors
9
a
and
9
b
which are connected at their drains to the sources of the pMOS transistors of the CMOS inverters
1
a
and
1
b
. The gates of the pMOS transistors
9
a
and
9
b
receive an input signal IN and a reference voltage VREF, respectively.
The power supply connection part
10
is connected at its drain to the sources of the pMOS transistors
8
a
,
8
b
,
9
a
, and
9
b
, is connected at its source to a power supply line VDD, and receives the clock signal /CLK at its gate. The buffer part
11
has inverters
11
a
and
11
b
for inverting the levels of the nodes ND
1
and ND
2
, respectively, and an output circuit
11
c
. The output circuit
11
c
has a pMOS transistor and an nMOS transistor arranged in series between the power supply line VDD and the ground line VSS. The gate of the pMOS transistor of the output circuit
11
c
is connected to the node /ND
1
. The gate of the nMOS transistor of the output circuit
11
c
is connected to the node /ND
2
through an inverter.
In the input circuit shown in
FIG. 2
, when the clock signal /CLK is at high level, the nMOS transistors
7
a
and
7
b
of the precharging part
7
turn on so that the input nodes ND
1
and ND
2
of the CMOS inverters
1
a
and
1
b
both change to low level. Then, the input signal IN is supplied before the clock signal /CLK changes to low level. Then, either one of the nodes ND
1
and ND
2
changes to high level, and the other to low level. Subsequently, in accordance with the voltages of the nodes ND
1
and ND
2
, either one of the pMOS transistors
8
a
and
8
b
of the feedback part
8
turns on so that the latching state is fixed until the c

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