Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2003-05-16
2004-05-11
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Format or disposition of elements
C365S053000, C365S230030, C365S230060
Reexamination Certificate
active
06735104
ABSTRACT:
BACKGROUND
Unlike memory cells of two-dimensional memory arrays, memory cells of vertically-stacked memory arrays are built above, rather than in, a planar substrate. These memory cells can be stacked vertically in numerous layers to form a three-dimensional array, as described in U.S. Pat. No. 6,034,882 to Johnson et al. The support circuits for vertically-stacked memory cells, such as row and column decoder circuits and wordline and bitline drivers, are on the surface of the substrate. While the support circuits can also be built above the substrate, the process complexity associated with stacking support circuits is currently too high for economical manufacturing. As a result, for very dense memory arrays, the support circuits occupy a very large percentage of the memory chip area. For example, support circuits can occupy half the area of a planar memory chip and an even larger percentage of a three-dimensional memory array stacked in 16 layers, even though the stacked memory cells occupy {fraction (1/16)} the area of conventional planar memory.
Several approaches have been described to provide a denser support circuit arrangement to obtain a smaller memory chip area. In an approach used with vertically-stacked memory arrays, row and/or column decoder circuits are disposed directly under the memory arrays to help minimize the fraction of the memory chip area not devoted to memory cells. This approach is described in U.S. Pat. No. 6,034,882 to Johnson et al. In an approach used with conventional two-dimensional memory arrays where support circuits are next to (but not below) the memory cells, row and column decoder circuits are shared between adjacent memory arrays. That is, the support circuits are associated with memory arrays on two sides of the support circuits but not above the support circuits. This approach is described in “The Design and Performance of CMOS 256 K Bit DRAM Devices” (see
FIG. 3
) and “A 288 K CMOS Pseudostatic RAM” (see
FIG. 3
) in the IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 5 (October 1984). With this approach, four times the number of memory arrays, for example, results in two times (not four times) the number of support circuits.
There is a need for a memory device with a denser support circuit arrangement.
SUMMARY
The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims.
By way of introduction, the preferred embodiments described below provide a memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
The preferred embodiments will now be described with reference to the attached drawings.
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Mohsen et al., “The Design and Performance of CMOS 256K Bit DRAM Devices,” IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, pp. 610-618 (Oct. 1984).
Kawamoto et al., “A 288K CMOS Pseudostatic RAM,” IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, pp. 619-623 (Oct. 1984).
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Ho Hoai
Matrix Semiconductor Inc.
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