Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
2001-09-11
2004-04-06
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S106000, C438S107000
Reexamination Certificate
active
06716674
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to a semiconductor package production method and a semiconductor package produced using said method.
BACKGROUND OF THE INVENTION
Conventionally, a Au—Si eutectic alloy, solder, and silver paste, for example, have been utilized as die attachment materials for bonding a semiconductor device (referred to also as a chip, hereinafter) to a bonding body, such as an interposing substrate, among the materials used for configuring a semiconductor package. Currently, as far as general-purpose and large-scale semiconductor packages are concerned, bonding using silver paste constitutes the mainstream in overall consideration of productivity, heat radiation, applicability to large-scale semiconductor devices, and price. The silver paste is applied to a bonding body, such as an interposing substrate, by means of a dispensing method, achieving excellent productivity since temporary crimping of semiconductor devices can be achieved easily. On the other hand, there was a problem that because it was liquid, control over the bonding thickness, coating positions, complete filling, and suppression of voids was difficult to achieve.
In recent years, surface terminal layout chip size packages (CSP, hereinafter) and ball grid arrays (BGA) have become popular in place of peripheral terminal layout type quad flat packages (QFP, hereinafter) and have made a great contribution in terms of weight reduction, thinning, and down-scaling of portable devices. The substrates utilized in such methods are referred to as interposing substrates in differentiation from the printed-circuit board to be actually installed. Because the structure is designed so that the size of the semiconductor device and the outer dimension of the semiconductor package are almost the same, the bond layer for bonding the semiconductor device to the interposing substrate is required to be free of overflow and insufficient filling and to have almost the same area as that of the semiconductor device.
In addition, because voids formed inside the bond layer significantly affect the moisture resistance reliability (resistance to corrosion of the wiring on the semiconductor device when unused for an extended period of time and subjected to moisture) and the antihygroscopic reflow characteristic (resistance to cracking and peeling inside the package caused when reflow soldering is applied after being unused for an extended period of time and subjected to moisture), elimination of voids in the bond layer is also demanded. Based on these points, a void-free film bond with high thickness accuracy and high positional accuracy while achieving productivity equivalent to that of the conventional paste bond has been in demand.
Die attachment utilizing a film bond is disclosed, for example, in Japanese Kokai Patent Application No. Sho 63[1988]-289822 and Japanese Kokai Patent Application No. Hei 1[1989]-19735. However, with the methods described in these patents, the film bond needed to be cut according to the size of a given semiconductor device first, many kinds of dies had to be prepared, and an expensive dedicated device was needed when pasting the film. Furthermore, a great portion of the film was wasted when it was worked to the size of the semiconductor device, and many kinds of slit products had to be prepared for each semiconductor device size in order to eliminate said waste film.
Thus, methods in which the wafer is diced into semiconductor devices with the bond after the film bond is pasted onto its back are shown, for example, in Japanese Kokai Patent Application No. Hei 11[1999]-219962 and Japanese Kokai Patent Application No. Hei 7[1995] 22440. However, the materials used for the film bonds described in these patents had problems in that because they had a high melt viscosity due to high polymer ratio, they needed to be laminated onto the wafer at a high temperature, that the dicing was dull, and that the die attachment required a high temperature, high pressure, and a long period of time. Although it is feasible to use a material containing an oligomer as the main ingredient for the bond layer in order to achieve low-temperature lamination, and although the lamination and die attachment can be achieved quickly at a low temperature and a low pressure using a material made primarily of oligomer, such as an epoxy resin, the problem that the dicing cannot be carried out continuously for a prolonged period of time due to the fouled dicing blade caused by melting of the resins during dicing has not yet been solved.
As a method for improving the temperature resistance cycle characteristic after being assembled into a package like a CSP and mounted onto a printed-circuit board, the point that the bond layer is to be made 100 &mgr;m thick or thicker is described in Japanese Kokai Patent Application No. 2000-31327; wherein a method in which bond layers are formed on both sides of a heat-resistant film serving as a base is shown as an example. However, although said method was superior in terms of the temperature resistance cycle characteristic, because it had poor dicing performance, a film bond with a film thickness of 100 &mgr;m or thicker was in demand in order to achieve high-level dicing performance.
Furthermore, because the surface mounted semiconductor packages, such as CSPs, were mounted onto both sides of the printed-circuit board, a high-level antihygroscopic reflow characteristic under high temperature, high humidity, and long-term moisture absorption condition was in demand. For example, in a mounting method utilizing a reflow furnace as a typical surface mounting technology (SMT), solder is melted using various heat sources, such as infrared rays, hot blasts, and lasers, for mounting; and reflow resistance during said operation was needed.
The purpose of the present invention is to present a semiconductor production method with an excellent dicing characteristic by which low-temperature die attachment can be achieved, and an excellent temperature resistance cycle characteristic and an antihygroscopic reflow characteristic can be attained after mounting onto a printed-circuit board, and to present a semiconductor package produced using said method.
SUMMARY OF THE INVENTION
The present inventors conducted investigations in order to achieve the aforementioned objective and found that the aforementioned problem can be solved by regulating the bond layer utilized particularly in the semiconductor production method, and thus completed the present invention.
That is, the present invention is a semiconductor package production method characterized as containing a step in which a bond layer made of a single-layer film thermoset bond is provided on the back of a wafer on which many semiconductor devices are formed in order to obtain a wafer with a bond layer, a step in which a dicing tape is pasted onto the bond layer's side of the wafer with the bond layer, and the bond layer and the wafer are diced simultaneously in order to obtain semiconductor devices with the bond layer, and a step in which the semiconductor devices with the bond layer are detached from the dicing tape and die-attached to interposing substrates serving as bodies to which they are bonded; wherein, the aforementioned bond layer made of the film thermoset bond is 100 &mgr;m thick or thicker, and the thermoset bond contains 50-80 wt % of spherical silica. It is desirable that the film thermoset bond utilized here essentially contains a glycidyl ether epoxy resin, an epoxy resin hardener, and a phenoxy resin. In addition, the present invention pertains also to semiconductor packages produced using the semiconductor package production method.
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Hatano Chihiro
Kirikae Noriyuki
Masumoto Mutsumi
Nishio Kimitaka
Yajima Kiyoshi
Brady III W. James
Lebentritt Michael S.
Smith Brad
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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